228 lines
7.8 KiB
Tcl
228 lines
7.8 KiB
Tcl
# Test comprehensive write_sdc / read_sdc / re-write roundtrip
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# Targets: WriteSdc.cc (all write* functions, WriteGet* classes),
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# Sdc.cc (reading constraints back in, net load/cap, voltage),
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# ExceptionPath.cc (exception comparison during merge),
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# Clock.cc (clock property persistence through roundtrip)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Create maximum variety of constraints
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############################################################
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# Clocks with different waveforms
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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create_clock -name vclk -period 8
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create_clock -name clk1_alt -period 5 -add [get_ports clk1]
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# Generated clocks
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create_generated_clock -name gclk_div -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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create_generated_clock -name gclk_mul -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
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create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
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# Propagated clock
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set_propagated_clock [get_clocks clk1]
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# Clock slew
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set_clock_transition -rise -max 0.15 [get_clocks clk1]
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set_clock_transition -fall -min 0.08 [get_clocks clk1]
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set_clock_transition 0.1 [get_clocks clk2]
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# Clock latency
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set_clock_latency -source 0.5 [get_clocks clk1]
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set_clock_latency -source -early 0.3 [get_clocks clk1]
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set_clock_latency -source -late 0.6 [get_clocks clk1]
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set_clock_latency -source -rise -max 0.65 [get_clocks clk1]
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set_clock_latency -source -fall -min 0.25 [get_clocks clk1]
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set_clock_latency 0.2 [get_clocks clk2]
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set_clock_latency -rise -max 0.4 [get_clocks clk2]
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set_clock_latency -fall -min 0.1 [get_clocks clk2]
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# Clock uncertainty (simple + inter-clock)
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set_clock_uncertainty -setup 0.2 [get_clocks clk1]
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set_clock_uncertainty -hold 0.1 [get_clocks clk1]
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
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# IO delays (various options)
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
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set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
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set_input_delay -clock clk2 1.8 [get_ports in3]
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set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3] -add_delay
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
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set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
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# Driving cells / input drive
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set_driving_cell -lib_cell BUF_X1 [get_ports in1]
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set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
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set_driving_cell -lib_cell BUF_X4 [get_ports in3]
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set_drive 100 [get_ports in1]
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set_drive -rise 80 [get_ports in2]
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set_drive -fall 120 [get_ports in2]
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# Loads
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set_load 0.05 [get_ports out1]
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set_load -pin_load 0.03 [get_ports out2]
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set_load -wire_load 0.02 [get_ports out1]
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# Input transitions
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set_input_transition 0.15 [get_ports in1]
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set_input_transition -rise -max 0.12 [get_ports in2]
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set_input_transition -fall -min 0.08 [get_ports in2]
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# Design limits
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set_max_transition 0.5 [current_design]
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set_max_capacitance 0.2 [current_design]
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set_max_fanout 20 [current_design]
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set_max_transition 0.3 [get_ports out1]
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set_max_capacitance 0.1 [get_ports out1]
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set_max_transition -clock_path 0.2 [get_clocks clk1]
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set_max_transition -data_path 0.4 [get_clocks clk1]
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set_max_area 100.0
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# False paths
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set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
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set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
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set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
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# Multicycle paths
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set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
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set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
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set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks gclk_div]
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# Max/min delay
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set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
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set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
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# Group paths
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group_path -name grp_clk1 -from [get_clocks clk1]
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group_path -name grp_io -from [get_ports in1] -to [get_ports out1]
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# Clock groups
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set_clock_groups -asynchronous -name async1 \
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-group {clk1 clk1_alt gclk_div gclk_edge} \
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-group {clk2 gclk_mul}
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# Clock sense
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set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
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# Disable timing
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set_disable_timing [get_cells buf1]
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
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# Case analysis
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set_case_analysis 0 [get_ports in3]
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# Logic values
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set_logic_one [get_ports in2]
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# Operating conditions
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set_operating_conditions typical
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# Wire load
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set_wire_load_model -name "5K_hvratio_1_1"
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set_wire_load_mode enclosed
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# Timing derate
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set_timing_derate -early 0.95
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set_timing_derate -late 1.05
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set_timing_derate -early -clock 0.97
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set_timing_derate -late -clock 1.03
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set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
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set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
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set_timing_derate -early -cell_delay 0.90 [get_cells buf1]
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set_timing_derate -late -cell_delay 1.10 [get_cells buf1]
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# Min pulse width
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set_min_pulse_width -high 0.6 [get_clocks clk1]
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set_min_pulse_width -low 0.4 [get_clocks clk1]
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# Latch borrow
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set_max_time_borrow 2.0 [get_clocks clk1]
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set_max_time_borrow 1.5 [get_pins reg1/D]
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# Clock gating check
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set_clock_gating_check -setup 0.5 [get_clocks clk1]
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set_clock_gating_check -hold 0.3 [get_clocks clk1]
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set_clock_gating_check -setup 0.4 [current_design]
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set_clock_gating_check -hold 0.2 [current_design]
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# Port fanout
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set_port_fanout_number 4 [get_ports out1]
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# Net resistance
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set_resistance -min 10.0 [get_nets n1]
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set_resistance -max 20.0 [get_nets n1]
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# Voltage
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set_voltage 1.1 -min 0.9
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# Data check
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set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
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set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
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############################################################
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# Write SDC in multiple formats
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############################################################
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set sdc_native [make_result_file sdc_roundtrip_native.sdc]
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write_sdc -no_timestamp $sdc_native
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set sdc_compat [make_result_file sdc_roundtrip_compat.sdc]
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write_sdc -no_timestamp -compatible $sdc_compat
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set sdc_d2 [make_result_file sdc_roundtrip_d2.sdc]
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write_sdc -no_timestamp -digits 2 $sdc_d2
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set sdc_d8 [make_result_file sdc_roundtrip_d8.sdc]
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write_sdc -no_timestamp -digits 8 $sdc_d8
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set sdc_hpins [make_result_file sdc_roundtrip_hpins.sdc]
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write_sdc -no_timestamp -map_hpins $sdc_hpins
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set sdc_compat_d6 [make_result_file sdc_roundtrip_compat_d6.sdc]
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write_sdc -no_timestamp -compatible -digits 6 $sdc_compat_d6
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report_checks
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############################################################
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# Read back native SDC (exercises read of all constraint types)
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############################################################
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# Re-read to exercise constraint merging
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read_sdc $sdc_native
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report_checks
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# Write again after re-read
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set sdc_rewrite [make_result_file sdc_roundtrip_rewrite.sdc]
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write_sdc -no_timestamp $sdc_rewrite
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############################################################
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# Read compatible SDC
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############################################################
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read_sdc $sdc_compat
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report_checks
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############################################################
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# Read high-precision SDC
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############################################################
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read_sdc $sdc_d8
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report_checks
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# Final write
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set sdc_final [make_result_file sdc_roundtrip_final.sdc]
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write_sdc -no_timestamp $sdc_final
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