62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
// Verilog design exercising preprocessor-like macro lines,
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// parameter declarations, parameter overrides (#(...) syntax),
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// defparam statements, and parameter expressions.
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// The lexer skips lines starting with ` (ifdef/endif/define/etc.)
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// Targets: VerilogLex.ll macro line skip, VerilogParse.yy parameter,
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// defparam, parameter_values (#(...)) in instance declarations.
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`define ENABLE_BUF 1
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`ifdef ENABLE_BUF
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`endif
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`ifndef DISABLE_INV
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`define WIDTH 4
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`else
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`endif
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module param_sub (input A, input B, output Y);
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parameter DELAY = 1;
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parameter MODE = "fast";
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AND2_X1 g1 (.A1(A), .A2(B), .ZN(Y));
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endmodule
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module verilog_preproc_param (clk, d1, d2, d3, d4,
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q1, q2, q3, q4);
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input clk;
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input d1, d2, d3, d4;
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output q1, q2, q3, q4;
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parameter TOP_WIDTH = 8;
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parameter [7:0] TOP_MASK = 8'hFF;
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parameter TOP_STR = "default";
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parameter TOP_EXPR = 2 * 3 + 1;
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wire n1, n2, n3, n4, n5, n6;
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`ifdef SOME_FEATURE
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// This block is skipped by the lexer
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`else
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// This block is also skipped
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`endif
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// Instance with parameter override using #(...)
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param_sub #(2) ps1 (.A(d1), .B(d2), .Y(n1));
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param_sub #(3) ps2 (.A(d3), .B(d4), .Y(n2));
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// Instance with parameter expression override
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param_sub #(1 + 1) ps3 (.A(d1), .B(d3), .Y(n3));
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// defparam statements
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defparam ps1.DELAY = 5;
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defparam ps2.DELAY = 10, ps2.MODE = "turbo";
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BUF_X1 buf1 (.A(n1), .Z(n4));
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INV_X1 inv1 (.A(n2), .ZN(n5));
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OR2_X1 or1 (.A1(n3), .A2(n4), .ZN(n6));
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DFF_X1 reg1 (.D(n4), .CK(clk), .Q(q1));
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DFF_X1 reg2 (.D(n5), .CK(clk), .Q(q2));
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DFF_X1 reg3 (.D(n6), .CK(clk), .Q(q3));
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DFF_X1 reg4 (.D(n1), .CK(clk), .Q(q4));
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endmodule
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