279 lines
9.3 KiB
Tcl
279 lines
9.3 KiB
Tcl
# Test SPICE write with GCD sky130hd design (larger design, more paths, bus signals)
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# Targets: WritePathSpice.cc (multi-stage paths, bus pin handling,
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# writeHeader, writePrintStmt, writeStageSubckts, writeInputSource,
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# writeMeasureStmts, drvr/load connection handling)
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# WriteSpice.cc (subckt file parsing with many cell types,
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# different cell topologies, NAND/NOR/INV/BUF/DFF/MUX cells,
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# readSubcktDef, readSubcktPinNames, spice model generation)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog spice_test2.v
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link_design spice_test2
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 1.0 [get_ports out1]
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set_output_delay -clock clk 1.0 [get_ports out2]
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set_input_transition 0.1 [get_ports {in1 in2}]
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# Read SPEF for parasitics (exercises parasitic path in spice write)
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# Use manual parasitics since we don't have matching SPEF
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sta::set_pi_model buf1/Z 0.002 5.0 0.001
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sta::set_elmore buf1/Z and1/A1 0.001
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sta::set_elmore buf1/Z or1/A1 0.001
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sta::set_pi_model inv1/ZN 0.002 5.0 0.001
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sta::set_elmore inv1/ZN and1/A2 0.001
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sta::set_elmore inv1/ZN or1/A2 0.001
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sta::set_pi_model and1/ZN 0.001 3.0 0.0005
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sta::set_elmore and1/ZN reg1/D 0.001
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sta::set_pi_model or1/ZN 0.001 3.0 0.0005
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sta::set_elmore or1/ZN reg2/D 0.001
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puts "--- report_checks ---"
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report_checks
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report_checks -path_delay min
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in2] -to [get_ports out2]
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# Create comprehensive mock SPICE files
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set spice_dir [make_result_file spice_multipath]
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file mkdir $spice_dir
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set model_file [file join $spice_dir model.sp]
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set model_fh [open $model_file w]
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puts $model_fh "* SPICE model file"
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puts $model_fh ".model nmos nmos level=3 tox=9e-9 vth0=0.7 gamma=0.5 phi=0.8 mu0=350"
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puts $model_fh ".model pmos pmos level=3 tox=9e-9 vth0=-0.7 gamma=0.4 phi=0.8 mu0=100"
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close $model_fh
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set subckt_file [file join $spice_dir subckt.sp]
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set subckt_fh [open $subckt_file w]
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puts $subckt_fh "* Subcircuit definitions"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt BUF_X1 A Z VDD VSS"
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puts $subckt_fh "M1 n1 A VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M2 n1 A VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh "M3 Z n1 VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M4 Z n1 VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt BUF_X2 A Z VDD VSS"
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puts $subckt_fh "M1 n1 A VSS VSS nmos W=0.4u L=0.1u"
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puts $subckt_fh "M2 n1 A VDD VDD pmos W=0.8u L=0.1u"
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puts $subckt_fh "M3 Z n1 VSS VSS nmos W=0.4u L=0.1u"
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puts $subckt_fh "M4 Z n1 VDD VDD pmos W=0.8u L=0.1u"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt INV_X1 A ZN VDD VSS"
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puts $subckt_fh "M1 ZN A VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M2 ZN A VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt AND2_X1 A1 A2 ZN VDD VSS"
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puts $subckt_fh "M1 n1 A1 VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M2 ZN A2 n1 VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M3 ZN A1 VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh "M4 ZN A2 VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt OR2_X1 A1 A2 ZN VDD VSS"
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puts $subckt_fh "M1 ZN A1 VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M2 ZN A2 VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh "M3 n1 A1 VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh "M4 ZN A2 n1 VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt DFF_X1 D CK Q QN VDD VSS"
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puts $subckt_fh "M1 Q D VDD VDD pmos W=0.4u L=0.1u"
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puts $subckt_fh "M2 Q D VSS VSS nmos W=0.2u L=0.1u"
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puts $subckt_fh ".ends"
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close $subckt_fh
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#---------------------------------------------------------------
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# write_path_spice with max path (default)
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#---------------------------------------------------------------
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puts "--- write_path_spice max ---"
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set spice_dir1 [make_result_file spice_mp_max]
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file mkdir $spice_dir1
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set rc1 [catch {
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_directory $spice_dir1 \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS
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} msg1]
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if { $rc1 == 0 } {
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} else {
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puts "INFO: write_path_spice max: $msg1"
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}
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#---------------------------------------------------------------
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# write_path_spice with min path
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#---------------------------------------------------------------
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puts "--- write_path_spice min ---"
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set spice_dir2 [make_result_file spice_mp_min]
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file mkdir $spice_dir2
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set rc2 [catch {
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write_path_spice \
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-path_args {-path_delay min} \
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-spice_directory $spice_dir2 \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS
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} msg2]
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if { $rc2 == 0 } {
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} else {
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puts "INFO: write_path_spice min: $msg2"
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}
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#---------------------------------------------------------------
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# write_path_spice with specific from/to
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#---------------------------------------------------------------
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puts "--- write_path_spice specific path ---"
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set spice_dir3 [make_result_file spice_mp_specific]
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file mkdir $spice_dir3
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set rc3 [catch {
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write_path_spice \
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-path_args {-from in1 -to out1} \
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-spice_directory $spice_dir3 \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS
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} msg3]
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if { $rc3 == 0 } {
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} else {
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puts "INFO: write_path_spice specific: $msg3"
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}
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#---------------------------------------------------------------
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# write_path_spice with hspice
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#---------------------------------------------------------------
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puts "--- write_path_spice hspice ---"
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set spice_dir4 [make_result_file spice_mp_hspice]
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file mkdir $spice_dir4
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set rc4 [catch {
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_directory $spice_dir4 \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS \
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-simulator hspice
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} msg4]
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if { $rc4 == 0 } {
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} else {
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puts "INFO: write_path_spice hspice: $msg4"
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}
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#---------------------------------------------------------------
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# write_path_spice with xyce
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#---------------------------------------------------------------
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puts "--- write_path_spice xyce ---"
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set spice_dir5 [make_result_file spice_mp_xyce]
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file mkdir $spice_dir5
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set rc5 [catch {
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_directory $spice_dir5 \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS \
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-simulator xyce
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} msg5]
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if { $rc5 == 0 } {
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} else {
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puts "INFO: write_path_spice xyce: $msg5"
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}
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#---------------------------------------------------------------
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# write_gate_spice with multiple cells and transitions
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#---------------------------------------------------------------
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puts "--- write_gate_spice multiple cells ---"
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# BUF rise
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set gf1 [file join $spice_dir gate_buf_rise.sp]
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set rc [catch {
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write_gate_spice -gates {{buf1 A Z rise}} -spice_filename $gf1 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS
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} msg]
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if { $rc == 0 } { puts "gate BUF rise" } else { puts "INFO: gate BUF rise: $msg" }
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# BUF fall
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set gf2 [file join $spice_dir gate_buf_fall.sp]
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set rc [catch {
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write_gate_spice -gates {{buf1 A Z fall}} -spice_filename $gf2 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS
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} msg]
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if { $rc == 0 } { puts "gate BUF fall" } else { puts "INFO: gate BUF fall: $msg" }
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# INV rise
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set gf3 [file join $spice_dir gate_inv_rise.sp]
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set rc [catch {
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write_gate_spice -gates {{inv1 A ZN rise}} -spice_filename $gf3 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS
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} msg]
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if { $rc == 0 } { puts "gate INV rise" } else { puts "INFO: gate INV rise: $msg" }
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# AND rise from A1
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set gf4 [file join $spice_dir gate_and_a1_rise.sp]
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set rc [catch {
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write_gate_spice -gates {{and1 A1 ZN rise}} -spice_filename $gf4 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS
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} msg]
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if { $rc == 0 } { puts "gate AND A1 rise" } else { puts "INFO: gate AND A1 rise: $msg" }
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# AND fall from A2
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set gf5 [file join $spice_dir gate_and_a2_fall.sp]
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set rc [catch {
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write_gate_spice -gates {{and1 A2 ZN fall}} -spice_filename $gf5 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS
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} msg]
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if { $rc == 0 } { puts "gate AND A2 fall" } else { puts "INFO: gate AND A2 fall: $msg" }
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# OR rise
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set gf6 [file join $spice_dir gate_or_rise.sp]
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set rc [catch {
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write_gate_spice -gates {{or1 A1 ZN rise}} -spice_filename $gf6 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS
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} msg]
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if { $rc == 0 } { puts "gate OR rise" } else { puts "INFO: gate OR rise: $msg" }
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# Hspice simulator variants
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set gf7 [file join $spice_dir gate_inv_hspice.sp]
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set rc [catch {
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write_gate_spice -gates {{inv1 A ZN fall}} -spice_filename $gf7 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS -simulator hspice
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} msg]
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if { $rc == 0 } { puts "gate INV hspice" } else { puts "INFO: gate INV hspice: $msg" }
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# Xyce simulator variants
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set gf8 [file join $spice_dir gate_or_xyce.sp]
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set rc [catch {
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write_gate_spice -gates {{or1 A2 ZN rise}} -spice_filename $gf8 \
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-lib_subckt_file $subckt_file -model_file $model_file \
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-power VDD -ground VSS -simulator xyce
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} msg]
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if { $rc == 0 } { puts "gate OR xyce" } else { puts "INFO: gate OR xyce: $msg" }
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