495 lines
16 KiB
Plaintext
495 lines
16 KiB
Plaintext
--- report_checks max through latch ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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--- report_checks min through latch ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.05 0.05 ^ latch1/Q (DLH_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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--- report_checks min_max ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.05 0.05 ^ latch1/Q (DLH_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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--- report_checks full_clock through latch ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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--- report_checks full_clock_expanded through latch ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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--- report_checks to latch output ---
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No paths found.
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--- report_checks from latch output ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.06 0.06 v latch1/Q (DLH_X1)
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0.00 0.06 v latch2/D (DLH_X1)
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0.06 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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0.06 0.06 time borrowed from endpoint
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0.06 data required time
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---------------------------------------------------------
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0.06 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 0.06
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--------------------------------------------
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--- report_check_types with latch ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.05 0.05 ^ latch1/Q (DLH_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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max slew
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Pin latch1/Q v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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max capacitance
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Pin latch1/Q ^
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max capacitance 60.58
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capacitance 2.05
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-----------------------
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Slack 58.52 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- check_setup with latch ---
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--- report_clock_skew ---
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Clock clk
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0.00 source latency latch1/G ^
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0.00 target latency latch2/G v
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0.00 CRPR
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--------------
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0.00 setup skew
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Clock clk
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0.00 source latency latch1/G ^
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0.00 target latency latch2/G v
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0.00 CRPR
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--------------
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0.00 hold skew
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency latch1/G
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0.00 network latency latch1/G
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency latch1/G
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0.00 network latency latch1/G
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_pulse_width_checks ---
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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5.00 open edge arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 reg1/CK
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0.00 10.00 clock reconvergence pessimism
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10.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (low)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Pin: latch1/G
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 latch1/G
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 latch1/G
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.04 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.96 slack (MET)
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Pin: latch2/G
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 latch2/G
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 latch2/G
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.04 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.96 slack (MET)
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--- find_timing_paths through latch ---
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Found 5 paths
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path to latch2/D slack=0.0
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path to latch2/D slack=0.0
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path to latch1/D slack=0.0
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path to latch1/D slack=0.0
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path to latch1/D slack=0.0
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--- all_registers with latch ---
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Register cells: 3
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latch1
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latch2
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reg1
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Level-sensitive cells: 2
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Edge-triggered cells: 1
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Data pins: 3
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Clock pins: 3
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Output pins: 4
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--- report_tns/report_wns with latch ---
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tns max 0.00
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wns max 0.00
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worst slack max 0.00
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worst slack min 0.05
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