19 lines
546 B
Verilog
19 lines
546 B
Verilog
module search_crpr (clk, in1, in2, out1);
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input clk, in1, in2;
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output out1;
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wire n1, n2, n3, n4, clk_buf1, clk_buf2;
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// Clock tree with reconvergence
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CLKBUF_X1 ckbuf1 (.A(clk), .Z(clk_buf1));
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CLKBUF_X1 ckbuf2 (.A(clk_buf1), .Z(clk_buf2));
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// Combinational logic
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AND2_X1 and1 (.A1(in1), .A2(in2), .ZN(n1));
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BUF_X1 buf1 (.A(n1), .Z(n2));
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// Two registers sharing reconvergent clock tree
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DFF_X1 reg1 (.D(n2), .CK(clk_buf1), .Q(n3));
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BUF_X1 buf2 (.A(n3), .Z(n4));
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DFF_X1 reg2 (.D(n4), .CK(clk_buf2), .Q(out1));
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endmodule
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