541 lines
17 KiB
Plaintext
541 lines
17 KiB
Plaintext
--- check_setup all flags ---
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Warning: There are 2 input ports missing set_input_delay.
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in3
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in_unconst
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Warning: There is 1 output port missing set_output_delay.
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out_unconst
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Warning: There are 2 unconstrained endpoints.
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out_unconst
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reg3/D
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--- check_setup -no_input_delay ---
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Warning: There are 2 input ports missing set_input_delay.
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in3
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in_unconst
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--- check_setup -no_output_delay ---
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Warning: There is 1 output port missing set_output_delay.
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out_unconst
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--- check_setup -no_clock ---
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--- check_setup -unconstrained_endpoints ---
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Warning: There are 2 unconstrained endpoints.
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out_unconst
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reg3/D
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--- check_setup -loops ---
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--- check_setup -generated_clocks ---
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--- check_setup multiple flags combined ---
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Warning: There are 2 input ports missing set_input_delay.
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in3
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in_unconst
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Warning: There is 1 output port missing set_output_delay.
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out_unconst
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Warning: There are 2 unconstrained endpoints.
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out_unconst
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reg3/D
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--- report_check_types all ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg2/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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max slew
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Pin reg1/QN v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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max capacitance
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Pin reg1/Q ^
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max capacitance 60.73
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capacitance 2.11
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-----------------------
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Slack 58.62 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- report_check_types individual ---
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Group Slack
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--------------------------------------------
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clk 7.90
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clk2 4.88
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Group Slack
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--------------------------------------------
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clk 1.04
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clk2 0.08
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.20 0.01 0.19 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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reg1/Q 60.73 2.11 58.62 (MET)
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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Group Slack
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--------------------------------------------
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No paths found.
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--- set_max_transition and check ---
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max slew
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Pin reg1/QN v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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--- set_max_capacitance and check ---
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max capacitance
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Pin reg1/Q ^
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max capacitance 0.05
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capacitance 2.11
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-----------------------
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Slack -2.06 (VIOLATED)
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--- set_max_fanout and check ---
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max fanout
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Pin reg1/Q
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max fanout 10
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fanout 2
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-----------------
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Slack 8 (MET)
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--- report_checks with unconstrained ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg2/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- set_clock_groups and check ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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-2.00 13.00 output external delay
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13.00 data required time
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---------------------------------------------------------
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13.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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12.90 slack (MET)
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Warning: There are 2 input ports missing set_input_delay.
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in3
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in_unconst
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Warning: There is 1 output port missing set_output_delay.
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out_unconst
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Warning: There are 2 unconstrained endpoints.
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out_unconst
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reg3/D
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--- report_clock_min_period ---
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clk period_min = 0.00 fmax = inf
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clk2 period_min = 0.00 fmax = inf
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clk period_min = 2.10 fmax = 475.37
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clk2 period_min = 2.10 fmax = 476.13
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clk period_min = 0.00 fmax = inf
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clk2 period_min = 0.00 fmax = inf
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--- Gated clock enable settings ---
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gated_clk_enable: 1
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg2/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- Gated clock check settings ---
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gated_clk_checks: 1
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg2/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- Recovery/removal checks ---
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recovery_removal: 1
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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15.00 15.00 clock clk2 (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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15.00 ^ reg2/CK (DFF_X1)
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-0.04 14.96 library setup time
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14.96 data required time
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---------------------------------------------------------
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14.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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4.88 slack (MET)
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--- Various STA variable settings ---
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preset_clr: 1
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cond_default: 1
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bidirect_inst: 1
|
|
bidirect_net: 1
|
|
dynamic_loop: 1
|
|
default_arrival_clk: 1
|