OpenSTA/sdc/test/sdc_genclk_advanced.ok

29 lines
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Clock Period Waveform
----------------------------------------------------
clk1 10.00 0.00 5.00
clk2 20.00 0.00 10.00
vclk 8.00 0.00 4.00
clk1_2x 5.00 0.00 2.50
clk_asym 12.00 0.00 3.00
Warning: generated clock gclk_div2 pin clk1 is in the fanout of multiple clocks.
Warning: generated clock gclk_div3 pin clk2 is in the fanout of multiple clocks.
Warning: generated clock gclk_mul2 pin clk1 is in the fanout of multiple clocks.
Clock Period Waveform
----------------------------------------------------
clk1 10.00 0.00 5.00
clk2 20.00 0.00 10.00
vclk 8.00 0.00 4.00
clk1_2x 5.00 0.00 2.50
clk_asym 12.00 0.00 3.00
gclk_div2 10.00 0.00 5.00 (generated)
gclk_div3 36.00 0.00 9.00 (generated)
gclk_mul2 2.50 0.00 1.25 (generated)
No paths found.
No paths found.
Clock Period Waveform
----------------------------------------------------
clk1 10.00 0.00 5.00
clk2 20.00 0.00 10.00
clk1_2x 5.00 0.00 2.50
clk_asym 12.00 0.00 3.00