245 lines
7.3 KiB
Plaintext
245 lines
7.3 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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--- Test 1: hierarchical pin queries ---
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buf_in/A: dir=input full_name=buf_in/A
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buf_in/Z: dir=output full_name=buf_in/Z
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inv1/A: dir=input full_name=inv1/A
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inv1/ZN: dir=output full_name=inv1/ZN
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reg1/D: dir=input full_name=reg1/D
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reg1/CK: dir=input full_name=reg1/CK
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reg1/Q: dir=output full_name=reg1/Q
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buf_out1/A: dir=input full_name=buf_out1/A
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buf_out1/Z: dir=output full_name=buf_out1/Z
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buf_out2/A: dir=input full_name=buf_out2/A
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buf_out2/Z: dir=output full_name=buf_out2/Z
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sub1/and_gate/A1: dir=input full_name=sub1/and_gate/A1
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sub1/and_gate/A2: dir=input full_name=sub1/and_gate/A2
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sub1/and_gate/ZN: dir=output full_name=sub1/and_gate/ZN
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sub1/buf_gate/A: dir=input full_name=sub1/buf_gate/A
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sub1/buf_gate/Z: dir=output full_name=sub1/buf_gate/Z
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sub2/and_gate/A1: dir=input full_name=sub2/and_gate/A1
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sub2/and_gate/A2: dir=input full_name=sub2/and_gate/A2
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sub2/and_gate/ZN: dir=output full_name=sub2/and_gate/ZN
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sub2/buf_gate/A: dir=input full_name=sub2/buf_gate/A
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sub2/buf_gate/Z: dir=output full_name=sub2/buf_gate/Z
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--- Test 2: pin classification ---
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buf_in/Z: is_driver=1 is_load=0 is_leaf=1
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inv1/ZN: is_driver=1 is_load=0 is_leaf=1
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reg1/Q: is_driver=1 is_load=0 is_leaf=1
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buf_out1/Z: is_driver=1 is_load=0 is_leaf=1
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buf_out2/Z: is_driver=1 is_load=0 is_leaf=1
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buf_in/A: is_driver=0 is_load=1 is_leaf=1
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inv1/A: is_driver=0 is_load=1 is_leaf=1
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reg1/D: is_driver=0 is_load=1 is_leaf=1
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reg1/CK: is_driver=0 is_load=1 is_leaf=1
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buf_out1/A: is_driver=0 is_load=1 is_leaf=1
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buf_out2/A: is_driver=0 is_load=1 is_leaf=1
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sub1/and_gate/A1: is_driver=0 is_load=1
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sub1/and_gate/ZN: is_driver=1 is_load=0
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sub1/buf_gate/Z: is_driver=1 is_load=0
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sub2/and_gate/A1: is_driver=0 is_load=1
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sub2/buf_gate/Z: is_driver=1 is_load=0
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port clk: dir=input
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port in1: dir=input
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port in2: dir=input
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port in3: dir=input
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port out1: dir=output
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port out2: dir=output
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--- Test 3: instance hierarchy ---
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inst buf_in: ref=BUF_X1 full_name=buf_in
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inst sub1: ref=sub_block full_name=sub1
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inst sub2: ref=sub_block full_name=sub2
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inst inv1: ref=INV_X1 full_name=inv1
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inst reg1: ref=DFF_X1 full_name=reg1
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inst buf_out1: ref=BUF_X2 full_name=buf_out1
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inst buf_out2: ref=BUF_X1 full_name=buf_out2
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inst sub1/and_gate: ref=AND2_X1 full_name=sub1/and_gate
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inst sub1/buf_gate: ref=BUF_X1 full_name=sub1/buf_gate
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inst sub2/and_gate: ref=AND2_X1 full_name=sub2/and_gate
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inst sub2/buf_gate: ref=BUF_X1 full_name=sub2/buf_gate
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buf_in ref=BUF_X1
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inv1 ref=INV_X1
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reg1 ref=DFF_X1
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sub1 ref=sub_block
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sub2 ref=sub_block
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--- Test 4: net hierarchy ---
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net w1: full_name=w1
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net w2: full_name=w2
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net w3: full_name=w3
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net w4: full_name=w4
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net w5: full_name=w5
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total hierarchical nets: 19
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Warning: network_hier_pin_query.tcl line 1, net 'sub1/*' not found.
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sub1/* nets: 0
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Warning: network_hier_pin_query.tcl line 1, net 'sub2/*' not found.
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sub2/* nets: 0
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--- Test 5: connected pins across hierarchy ---
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net w1 has 2 pins
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net w2 has 2 pins
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net w3 has 3 pins
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net w4 has 2 pins
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net w5 has 2 pins
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Net w1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_in/Z output (BUF_X1)
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Load pins
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sub1/and_gate/A1 input (AND2_X1) 0.87-0.92
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Hierarchical pins
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sub1/A input
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Net w2
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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sub1/buf_gate/Z output (BUF_X1)
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Load pins
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sub2/and_gate/A1 input (AND2_X1) 0.87-0.92
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Hierarchical pins
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sub1/Y output
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sub2/A input
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Net w3
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Pin capacitance: 2.42-2.67
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Wire capacitance: 0.00
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Total capacitance: 2.42-2.67
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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sub2/buf_gate/Z output (BUF_X1)
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Load pins
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buf_out2/A input (BUF_X1) 0.88-0.97
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inv1/A input (INV_X1) 1.55-1.70
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Hierarchical pins
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sub2/Y output
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--- Test 6: pin pattern matching ---
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flat */* pins: 20
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hier * pins: 30
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sub1/* pins: 3
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hier sub*/* pins: 6
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hier *and*/* pins: 6
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hier *buf*/* pins: 10
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--- Test 7: timing through hierarchy ---
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No paths found.
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No paths found.
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Startpoint: in3 (input port clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.06 0.06 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.09 v sub2/buf_gate/Z (BUF_X1)
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0.02 0.11 v buf_out2/Z (BUF_X1)
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0.00 0.11 v out2 (out)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.89 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.02 0.18 v buf_out2/Z (BUF_X1)
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0.00 0.18 v out2 (out)
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0.18 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.18 data arrival time
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---------------------------------------------------------
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9.82 slack (MET)
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No paths found.
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--- Test 8: fanin/fanout ---
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fanin to out1 flat: 5
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fanin to out1 cells: 3
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fanout from in1 flat: 17
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fanout from in1 endpoints: 0
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fanin to out2 flat: 18
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fanout from in3 flat: 11
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