177 lines
6.3 KiB
Tcl
177 lines
6.3 KiB
Tcl
# Test write_sdc paths for disabled ports, clock groups, group paths,
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# output drives, inter-clock uncertainty, and min pulse width writing.
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# Targets:
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# WriteSdc.cc: writeDisabledPorts (disabled top-level ports),
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# writeDisabledInstances (disabled instances with from/to),
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# writeFalsePaths (false_path writing with setup/hold),
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# writeExceptionThruPins/Nets/Instances,
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# writeGroupPath (named and default, with weight being ignored),
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# writeOutputDrives (set_driving_cell, set_drive),
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# writeMinPulseWidths (on design/clock/pin/instance),
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# writePortExtCap (pin/wire/fanout writing),
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# writeInterClockUncertainty (all rise/fall/setup/hold combos),
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# writeClockGroups (async/logically_excl/physically_excl),
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# writePropagatedClkPins, writeClockInsertions,
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# writeClockSenses
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# Sdc.cc: various getter functions exercised during write
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 [get_ports clk2]
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create_clock -name vclk -period 8
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.0 [get_ports in2]
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set_input_delay -clock clk2 2.0 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 3.0 [get_ports out2]
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# Disable timing on ports (exercises writeDisabledPorts)
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set_disable_timing [get_ports in1]
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set_disable_timing [get_ports in2]
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# Disable timing on instances with from/to (exercises writeDisabledInstances)
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set_disable_timing [get_cells buf1]
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set_disable_timing [get_cells inv1]
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# Disable on instance with from/to pins
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set_disable_timing -from A -to ZN [get_cells inv1]
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# Disable on lib cell (exercises writeDisabledCells)
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/OR2_X1]
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# Disable on pins
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set_disable_timing [get_pins nand1/A1]
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# Write with disables
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set sdc1 [make_result_file sdc_wdg1.sdc]
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write_sdc -no_timestamp $sdc1
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# Unset disables
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unset_disable_timing [get_ports in1]
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unset_disable_timing [get_ports in2]
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unset_disable_timing [get_cells buf1]
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unset_disable_timing [get_cells inv1]
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/OR2_X1]
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unset_disable_timing [get_pins nand1/A1]
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# Clock groups - all three types (exercises writeClockGroups)
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set_clock_groups -asynchronous -name async1 -group {clk1} -group {clk2}
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set sdc2 [make_result_file sdc_wdg2.sdc]
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write_sdc -no_timestamp $sdc2
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unset_clock_groups -asynchronous -name async1
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set_clock_groups -logically_exclusive -name logic1 -group {clk1} -group {clk2}
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set sdc3 [make_result_file sdc_wdg3.sdc]
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write_sdc -no_timestamp $sdc3
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unset_clock_groups -logically_exclusive -name logic1
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set_clock_groups -physically_exclusive -name phys1 -group {clk1} -group {vclk}
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set sdc4 [make_result_file sdc_wdg4.sdc]
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write_sdc -no_timestamp $sdc4
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unset_clock_groups -physically_exclusive -name phys1
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# Group paths - named and default (exercises writeGroupPath)
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group_path -name grp_reg -from [get_clocks clk1] -to [get_clocks clk1]
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group_path -name grp_cross -from [get_clocks clk1] -to [get_clocks clk2]
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group_path -default -from [get_ports in1] -to [get_ports out1]
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# Group path with weight (weight is ignored but syntax is accepted)
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group_path -name grp_weighted -weight 2.0 \
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-from [get_ports in2] -to [get_ports out2]
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# Group path with through
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group_path -name grp_thru -from [get_ports in1] \
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-through [get_pins buf1/Z] \
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-through [get_pins and1/ZN] \
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-to [get_ports out1]
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# Output drives (exercises writeOutputDrives/writeDriveResistances)
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set_driving_cell -lib_cell BUF_X1 [get_ports in1]
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set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
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set_driving_cell -lib_cell BUF_X4 [get_ports in3]
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set_drive 100 [get_ports in1]
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set_drive -rise 80 [get_ports in2]
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set_drive -fall 120 [get_ports in2]
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# Input transition
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set_input_transition 0.15 [get_ports in1]
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set_input_transition -rise -max 0.12 [get_ports in2]
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set_input_transition -fall -min 0.08 [get_ports in2]
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# Inter-clock uncertainty with all combinations
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# (exercises writeInterClockUncertainty)
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
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# Min pulse width on multiple target types
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# (exercises writeMinPulseWidths)
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set_min_pulse_width 0.5
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set_min_pulse_width -high 0.6 [get_clocks clk1]
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set_min_pulse_width -low 0.4 [get_clocks clk1]
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set_min_pulse_width 0.55 [get_clocks clk2]
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set_min_pulse_width 0.3 [get_pins reg1/CK]
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set_min_pulse_width 0.45 [get_cells reg3]
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# Port loads (exercises writePortLoads/writePortExtCap)
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set_load -pin_load 0.05 [get_ports out1]
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set_load -wire_load 0.02 [get_ports out1]
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set_load -pin_load -rise 0.04 [get_ports out2]
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set_load -pin_load -fall 0.045 [get_ports out2]
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set_port_fanout_number 4 [get_ports out1]
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# Clock sense (exercises writeClockSenses)
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set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
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set_clock_sense -negative -clocks [get_clocks clk2] [get_pins or1/ZN]
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# Propagated clocks (exercises writePropagatedClkPins)
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set_propagated_clock [get_clocks clk1]
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set_propagated_clock [get_ports clk2]
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# Clock insertion (exercises writeClockInsertions)
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set_clock_latency -source -early 0.3 [get_clocks clk1]
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set_clock_latency -source -late 0.5 [get_clocks clk1]
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# Clock transition
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set_clock_transition -rise -max 0.15 [get_clocks clk1]
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set_clock_transition -fall -min 0.08 [get_clocks clk1]
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set_clock_transition 0.1 [get_clocks clk2]
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# False paths with -setup/-hold only
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# (exercises writeFalsePaths branches)
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set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
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set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
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# Comprehensive write with all constraint types
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set sdc5 [make_result_file sdc_wdg5.sdc]
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write_sdc -no_timestamp $sdc5
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set sdc6 [make_result_file sdc_wdg6.sdc]
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write_sdc -no_timestamp -compatible $sdc6
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set sdc7 [make_result_file sdc_wdg7.sdc]
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write_sdc -no_timestamp -digits 8 $sdc7
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set sdc8 [make_result_file sdc_wdg8.sdc]
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write_sdc -no_timestamp -map_hpins $sdc8
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report_checks
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