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# ccs_sim parallel inverters
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read_liberty asap7_invbuf.lib.gz
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read_verilog ccs_sim1.v
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link_design top
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read_spef ccs_sim1.spef
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set_input_transition 20 in1
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sta::set_delay_calculator ccs_sim
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report_checks -fields {input_pins slew} -unconstrained -digits 3
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