71 lines
2.2 KiB
Plaintext
71 lines
2.2 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.02 0.02 v buf1/Z (BUF_X1)
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0.02 0.05 v and1/ZN (AND2_X1)
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0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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--- make_instance using liberty cell ---
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lib_buf pins: 2
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pin: lib_buf/A dir=input
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pin: lib_buf/Z dir=output
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--- fanin/fanout on new cells ---
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fanin to lib_buf/Z: 2
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fanout from lib_buf/A: 2
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--- disconnect and reconnect ---
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--- multiple instance creation ---
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total cells after add: 6
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test_* cells: 3
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total cells after delete: 3
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--- replace_cell tests ---
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replace_cell buf1 -> BUF_X4: 1
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buf1 ref after replace: BUF_X4
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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