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OpenSTA/verilog
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dsengupta0628 3b8e81393d Merge branch 'master' into sta_latest_from_parallaxsw_0407 2026-04-07 21:53:36 +00:00
..
test Fix report_checks -fields {nets} typo to {net} across test scripts 2026-04-06 14:41:40 +09:00
Verilog.i update copyright 2026-03-10 14:57:45 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll string squash 2026-03-28 19:13:35 -07:00
VerilogParse.yy string squash 2026-03-28 19:13:35 -07:00
VerilogReader.cc string squash 2026-03-28 19:13:35 -07:00
VerilogReaderPvt.hh string squash 2026-03-28 19:13:35 -07:00
VerilogScanner.hh string squash 2026-03-28 19:13:35 -07:00
VerilogWriter.cc Bias pin handling (#409) 2026-04-07 11:00:01 -07:00