15 lines
444 B
Tcl
15 lines
444 B
Tcl
# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
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read_liberty gf180mcu_sram.lib.gz
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read_liberty asap7_small.lib.gz
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read_verilog test_write_verilog_escape.v
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link_design multi_sink
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write_verilog test_write_verilog_escape_out.v
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set input_file "test_write_verilog_escape_out.v"
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set fp [open $input_file r]
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while {[gets $fp line] >= 0} {
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puts $line
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}
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close $fp
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file delete "test_write_verilog_escape_out.v"
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