102453 lines
2.2 MiB
102453 lines
2.2 MiB
/**
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* Copyright 2020 The SkyWater PDK Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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`ifndef SKY130_FD_SC_HD__A2BB2O_V
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`define SKY130_FD_SC_HD__A2BB2O_V
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/**
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* a2bb2o: 2-input AND, both inputs inverted, into first input, and
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* 2-input AND into 2nd input of 2-input OR.
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*
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* X = ((!A1 & !A2) | (B1 & B2))
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*
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* Verilog top module.
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*
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* WARNING: This file is autogenerated, do not modify directly!
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*/
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`timescale 1ns / 1ps
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`default_nettype none
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`ifdef USE_POWER_PINS
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`ifdef FUNCTIONAL
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/*
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* Copyright 2020 The SkyWater PDK Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
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`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
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/**
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* a2bb2o: 2-input AND, both inputs inverted, into first input, and
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* 2-input AND into 2nd input of 2-input OR.
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*
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* X = ((!A1 & !A2) | (B1 & B2))
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*
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* Verilog simulation functional model.
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*/
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`timescale 1ns / 1ps
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`default_nettype none
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// Import user defined primitives.
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`celldefine
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module sky130_fd_sc_hd__a2bb2o (
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X ,
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A1_N,
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A2_N,
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B1 ,
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B2 ,
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VPWR,
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VGND,
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VPB ,
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VNB
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);
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// Module ports
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output X ;
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input A1_N;
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input A2_N;
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input B1 ;
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input B2 ;
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input VPWR;
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input VGND;
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input VPB ;
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input VNB ;
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// Local signals
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wire and0_out ;
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wire nor0_out ;
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wire or0_out_X ;
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wire pwrgood_pp0_out_X;
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// Name Output Other arguments
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and and0 (and0_out , B1, B2 );
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nor nor0 (nor0_out , A1_N, A2_N );
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or or0 (or0_out_X , nor0_out, and0_out );
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sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
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buf buf0 (X , pwrgood_pp0_out_X );
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endmodule
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`endcelldefine
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`default_nettype wire
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`endif // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_PP_V
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`else // FUNCTIONAL
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/*
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* Copyright 2020 The SkyWater PDK Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
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`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
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/**
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* a2bb2o: 2-input AND, both inputs inverted, into first input, and
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* 2-input AND into 2nd input of 2-input OR.
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*
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* X = ((!A1 & !A2) | (B1 & B2))
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*
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* Verilog simulation functional model.
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*/
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`timescale 1ns / 1ps
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`default_nettype none
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// Import user defined primitives.
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`celldefine
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module sky130_fd_sc_hd__a2bb2o (
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X ,
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A1_N,
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A2_N,
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B1 ,
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B2 ,
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VPWR,
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VGND,
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VPB ,
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VNB
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);
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// Module ports
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output X ;
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input A1_N;
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input A2_N;
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input B1 ;
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input B2 ;
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input VPWR;
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input VGND;
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input VPB ;
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input VNB ;
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// Local signals
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wire and0_out ;
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wire nor0_out ;
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wire or0_out_X ;
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wire pwrgood_pp0_out_X;
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// Name Output Other arguments
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and and0 (and0_out , B1, B2 );
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nor nor0 (nor0_out , A1_N, A2_N );
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or or0 (or0_out_X , nor0_out, and0_out );
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sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
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buf buf0 (X , pwrgood_pp0_out_X );
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endmodule
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`endcelldefine
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`default_nettype wire
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`endif // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_PP_V
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`endif // FUNCTIONAL
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`else // USE_POWER_PINS
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`ifdef FUNCTIONAL
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/*
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* Copyright 2020 The SkyWater PDK Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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|
* distributed under the License is distributed on an "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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`ifndef SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
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`define SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
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/**
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* a2bb2o: 2-input AND, both inputs inverted, into first input, and
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* 2-input AND into 2nd input of 2-input OR.
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*
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* X = ((!A1 & !A2) | (B1 & B2))
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*
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* Verilog simulation functional model.
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*/
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`timescale 1ns / 1ps
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`default_nettype none
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`celldefine
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module sky130_fd_sc_hd__a2bb2o (
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X ,
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A1_N,
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A2_N,
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B1 ,
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B2
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);
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// Module ports
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output X ;
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input A1_N;
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input A2_N;
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input B1 ;
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input B2 ;
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// Local signals
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wire and0_out ;
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wire nor0_out ;
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wire or0_out_X;
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// Name Output Other arguments
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and and0 (and0_out , B1, B2 );
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nor nor0 (nor0_out , A1_N, A2_N );
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or or0 (or0_out_X, nor0_out, and0_out);
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buf buf0 (X , or0_out_X );
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endmodule
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`endcelldefine
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`default_nettype wire
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`endif // SKY130_FD_SC_HD__A2BB2O_FUNCTIONAL_V
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`else // FUNCTIONAL
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/*
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* Copyright 2020 The SkyWater PDK Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
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*
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* https://www.apache.org/licenses/LICENSE-2.0
|
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*
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|
* Unless required by applicable law or agreed to in writing, software
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|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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`ifndef SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
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`define SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
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/**
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* a2bb2o: 2-input AND, both inputs inverted, into first input, and
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* 2-input AND into 2nd input of 2-input OR.
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*
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* X = ((!A1 & !A2) | (B1 & B2))
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*
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* Verilog simulation functional model.
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*/
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`timescale 1ns / 1ps
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`default_nettype none
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`celldefine
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module sky130_fd_sc_hd__a2bb2o (
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X ,
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A1_N,
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A2_N,
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B1 ,
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B2
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);
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// Module ports
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output X ;
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input A1_N;
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input A2_N;
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input B1 ;
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input B2 ;
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// Module supplies
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supply1 VPWR;
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supply0 VGND;
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supply1 VPB ;
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supply0 VNB ;
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// Local signals
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wire and0_out ;
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wire nor0_out ;
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wire or0_out_X;
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// Name Output Other arguments
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and and0 (and0_out , B1, B2 );
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nor nor0 (nor0_out , A1_N, A2_N );
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or or0 (or0_out_X, nor0_out, and0_out);
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buf buf0 (X , or0_out_X );
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endmodule
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`endcelldefine
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`default_nettype wire
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`endif // SKY130_FD_SC_HD__A2BB2O_BEHAVIORAL_V
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`endif // FUNCTIONAL
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`endif // USE_POWER_PINS
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`default_nettype wire
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`endif // SKY130_FD_SC_HD__A2BB2O_V
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//--------EOF---------
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/**
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* Copyright 2020 The SkyWater PDK Authors
|
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*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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`ifndef SKY130_FD_SC_HD__A2BB2O_1_V
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`define SKY130_FD_SC_HD__A2BB2O_1_V
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/**
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* a2bb2o: 2-input AND, both inputs inverted, into first input, and
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* 2-input AND into 2nd input of 2-input OR.
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|
*
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* X = ((!A1 & !A2) | (B1 & B2))
|
|
*
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|
* Verilog wrapper for a2bb2o with size of 1 units.
|
|
*
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|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
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`timescale 1ns / 1ps
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`default_nettype none
|
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|
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`ifdef USE_POWER_PINS
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/*********************************************************/
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`celldefine
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module sky130_fd_sc_hd__a2bb2o_1 (
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X ,
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A1_N,
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A2_N,
|
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B1 ,
|
|
B2 ,
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|
VPWR,
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|
VGND,
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VPB ,
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VNB
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);
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output X ;
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input A1_N;
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input A2_N;
|
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input B1 ;
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input B2 ;
|
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input VPWR;
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input VGND;
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input VPB ;
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input VNB ;
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sky130_fd_sc_hd__a2bb2o base (
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.X(X),
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.A1_N(A1_N),
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.A2_N(A2_N),
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.B1(B1),
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.B2(B2),
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.VPWR(VPWR),
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.VGND(VGND),
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.VPB(VPB),
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.VNB(VNB)
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);
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endmodule
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`endcelldefine
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/*********************************************************/
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`else // If not USE_POWER_PINS
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/*********************************************************/
|
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`celldefine
|
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module sky130_fd_sc_hd__a2bb2o_1 (
|
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X ,
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A1_N,
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A2_N,
|
|
B1 ,
|
|
B2
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|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
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|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2bb2o base (
|
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.X(X),
|
|
.A1_N(A1_N),
|
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.A2_N(A2_N),
|
|
.B1(B1),
|
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.B2(B2)
|
|
);
|
|
|
|
endmodule
|
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`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2O_2_V
|
|
`define SKY130_FD_SC_HD__A2BB2O_2_V
|
|
|
|
/**
|
|
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input OR.
|
|
*
|
|
* X = ((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a2bb2o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2o_2 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2bb2o base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2o_2 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2bb2o base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2O_4_V
|
|
`define SKY130_FD_SC_HD__A2BB2O_4_V
|
|
|
|
/**
|
|
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input OR.
|
|
*
|
|
* X = ((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a2bb2o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2o_4 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2bb2o base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2o_4 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2bb2o base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
nor nor0 (nor0_out , A1_N, A2_N );
|
|
nor nor1 (nor1_out_Y , nor0_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
nor nor0 (nor0_out , A1_N, A2_N );
|
|
nor nor1 (nor1_out_Y , nor0_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
nor nor0 (nor0_out , A1_N, A2_N );
|
|
nor nor1 (nor1_out_Y, nor0_out, and0_out);
|
|
buf buf0 (Y , nor1_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
nor nor0 (nor0_out , A1_N, A2_N );
|
|
nor nor1 (nor1_out_Y, nor0_out, and0_out);
|
|
buf buf0 (Y , nor1_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_1_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_1_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a2bb2oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi_1 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2bb2oi base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi_1 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2bb2oi base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_2_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_2_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a2bb2oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi_2 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2bb2oi base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi_2 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2bb2oi base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2BB2OI_4_V
|
|
`define SKY130_FD_SC_HD__A2BB2OI_4_V
|
|
|
|
/**
|
|
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
|
|
* 2-input AND into 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((!A1 & !A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a2bb2oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi_4 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2bb2oi base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2bb2oi_4 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2bb2oi base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2BB2OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_V
|
|
`define SKY130_FD_SC_HD__A21BO_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out_X , B1_N, nand0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out_X , B1_N, nand0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out_X, B1_N, nand0_out);
|
|
buf buf0 (X , nand1_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out_X, B1_N, nand0_out);
|
|
buf buf0 (X , nand1_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_1_V
|
|
`define SKY130_FD_SC_HD__A21BO_1_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21bo with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21bo base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21bo base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_2_V
|
|
`define SKY130_FD_SC_HD__A21BO_2_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21bo with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21bo base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21bo base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BO_4_V
|
|
`define SKY130_FD_SC_HD__A21BO_4_V
|
|
|
|
/**
|
|
* a21bo: 2-input AND into first input of 2-input OR,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21bo with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21bo base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21bo_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21bo base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BO_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_V
|
|
`define SKY130_FD_SC_HD__A21BOI_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , b, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , b, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, b, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, b, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_0_V
|
|
`define SKY130_FD_SC_HD__A21BOI_0_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21boi with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_0 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_0 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_1_V
|
|
`define SKY130_FD_SC_HD__A21BOI_1_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21boi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_2_V
|
|
`define SKY130_FD_SC_HD__A21BOI_2_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21boi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21BOI_4_V
|
|
`define SKY130_FD_SC_HD__A21BOI_4_V
|
|
|
|
/**
|
|
* a21boi: 2-input AND into first input of 2-input NOR,
|
|
* 2nd input inverted.
|
|
*
|
|
* Y = !((A1 & A2) | (!B1_N))
|
|
*
|
|
* Verilog wrapper for a21boi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21boi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21boi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21BOI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_V
|
|
`define SKY130_FD_SC_HD__A21O_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X , and0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X , and0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X, and0_out, B1 );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X, and0_out, B1 );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_1_V
|
|
`define SKY130_FD_SC_HD__A21O_1_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog wrapper for a21o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_2_V
|
|
`define SKY130_FD_SC_HD__A21O_2_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog wrapper for a21o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21O_4_V
|
|
`define SKY130_FD_SC_HD__A21O_4_V
|
|
|
|
/**
|
|
* a21o: 2-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1)
|
|
*
|
|
* Verilog wrapper for a21o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_V
|
|
`define SKY130_FD_SC_HD__A21OI_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , B1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , B1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, B1, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, B1, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_1_V
|
|
`define SKY130_FD_SC_HD__A21OI_1_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog wrapper for a21oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_2_V
|
|
`define SKY130_FD_SC_HD__A21OI_2_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog wrapper for a21oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A21OI_4_V
|
|
`define SKY130_FD_SC_HD__A21OI_4_V
|
|
|
|
/**
|
|
* a21oi: 2-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1)
|
|
*
|
|
* Verilog wrapper for a21oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a21oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a21oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a21oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A21OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_V
|
|
`define SKY130_FD_SC_HD__A22O_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X, and1_out, and0_out);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X, and1_out, and0_out);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_1_V
|
|
`define SKY130_FD_SC_HD__A22O_1_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a22o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a22o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a22o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_2_V
|
|
`define SKY130_FD_SC_HD__A22O_2_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a22o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a22o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a22o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22O_4_V
|
|
`define SKY130_FD_SC_HD__A22O_4_V
|
|
|
|
/**
|
|
* a22o: 2-input AND into both inputs of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a22o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a22o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a22o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_V
|
|
`define SKY130_FD_SC_HD__A22OI_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y , nand0_out, nand1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y , nand0_out, nand1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y, nand0_out, nand1_out);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y, nand0_out, nand1_out);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_1_V
|
|
`define SKY130_FD_SC_HD__A22OI_1_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a22oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a22oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a22oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_2_V
|
|
`define SKY130_FD_SC_HD__A22OI_2_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a22oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a22oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a22oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A22OI_4_V
|
|
`define SKY130_FD_SC_HD__A22OI_4_V
|
|
|
|
/**
|
|
* a22oi: 2-input AND into both inputs of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a22oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a22oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a22oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a22oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A22OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_V
|
|
`define SKY130_FD_SC_HD__A31O_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X , and0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X , and0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X, and0_out, B1 );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X, and0_out, B1 );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_1_V
|
|
`define SKY130_FD_SC_HD__A31O_1_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog wrapper for a31o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a31o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a31o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_2_V
|
|
`define SKY130_FD_SC_HD__A31O_2_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog wrapper for a31o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a31o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a31o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31O_4_V
|
|
`define SKY130_FD_SC_HD__A31O_4_V
|
|
|
|
/**
|
|
* a31o: 3-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog wrapper for a31o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a31o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a31o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_V
|
|
`define SKY130_FD_SC_HD__A31OI_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y , B1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y , B1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y, B1, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y, B1, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_1_V
|
|
`define SKY130_FD_SC_HD__A31OI_1_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog wrapper for a31oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a31oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a31oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_2_V
|
|
`define SKY130_FD_SC_HD__A31OI_2_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog wrapper for a31oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a31oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a31oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A31OI_4_V
|
|
`define SKY130_FD_SC_HD__A31OI_4_V
|
|
|
|
/**
|
|
* a31oi: 3-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1)
|
|
*
|
|
* Verilog wrapper for a31oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a31oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a31oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a31oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A31OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_V
|
|
`define SKY130_FD_SC_HD__A32O_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
and and1 (and1_out , B1, B2 );
|
|
or or0 (or0_out_X , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
and and1 (and1_out , B1, B2 );
|
|
or or0 (or0_out_X , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
and and1 (and1_out , B1, B2 );
|
|
or or0 (or0_out_X, and1_out, and0_out);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
and and1 (and1_out , B1, B2 );
|
|
or or0 (or0_out_X, and1_out, and0_out);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_1_V
|
|
`define SKY130_FD_SC_HD__A32O_1_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a32o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a32o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a32o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_2_V
|
|
`define SKY130_FD_SC_HD__A32O_2_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a32o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a32o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a32o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32O_4_V
|
|
`define SKY130_FD_SC_HD__A32O_4_V
|
|
|
|
/**
|
|
* a32o: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a32o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a32o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a32o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_V
|
|
`define SKY130_FD_SC_HD__A32OI_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1, A3 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y , nand0_out, nand1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1, A3 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y , nand0_out, nand1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1, A3 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y, nand0_out, nand1_out);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1, A3 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
and and0 (and0_out_Y, nand0_out, nand1_out);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_1_V
|
|
`define SKY130_FD_SC_HD__A32OI_1_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a32oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a32oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a32oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_2_V
|
|
`define SKY130_FD_SC_HD__A32OI_2_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a32oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a32oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a32oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A32OI_4_V
|
|
`define SKY130_FD_SC_HD__A32OI_4_V
|
|
|
|
/**
|
|
* a32oi: 3-input AND into first input, and 2-input AND into
|
|
* 2nd input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | (B1 & B2))
|
|
*
|
|
* Verilog wrapper for a32oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a32oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a32oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a32oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A32OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_V
|
|
`define SKY130_FD_SC_HD__A41O_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
or or0 (or0_out_X , and0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
or or0 (or0_out_X , and0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
or or0 (or0_out_X, and0_out, B1 );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
or or0 (or0_out_X, and0_out, B1 );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_1_V
|
|
`define SKY130_FD_SC_HD__A41O_1_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog wrapper for a41o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a41o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a41o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_2_V
|
|
`define SKY130_FD_SC_HD__A41O_2_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog wrapper for a41o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a41o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a41o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41O_4_V
|
|
`define SKY130_FD_SC_HD__A41O_4_V
|
|
|
|
/**
|
|
* a41o: 4-input AND into first input of 2-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog wrapper for a41o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a41o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a41o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_V
|
|
`define SKY130_FD_SC_HD__A41OI_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
nor nor0 (nor0_out_Y , B1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
nor nor0 (nor0_out_Y , B1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
nor nor0 (nor0_out_Y, B1, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2, A3, A4 );
|
|
nor nor0 (nor0_out_Y, B1, and0_out );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_1_V
|
|
`define SKY130_FD_SC_HD__A41OI_1_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog wrapper for a41oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a41oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a41oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_2_V
|
|
`define SKY130_FD_SC_HD__A41OI_2_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog wrapper for a41oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a41oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a41oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A41OI_4_V
|
|
`define SKY130_FD_SC_HD__A41OI_4_V
|
|
|
|
/**
|
|
* a41oi: 4-input AND into first input of 2-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3 & A4) | B1)
|
|
*
|
|
* Verilog wrapper for a41oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a41oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a41oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a41oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A41OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_V
|
|
`define SKY130_FD_SC_HD__A211O_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X , and0_out, C1, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X , and0_out, C1, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X, and0_out, C1, B1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X, and0_out, C1, B1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_1_V
|
|
`define SKY130_FD_SC_HD__A211O_1_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a211o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a211o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a211o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_2_V
|
|
`define SKY130_FD_SC_HD__A211O_2_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a211o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a211o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a211o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211O_4_V
|
|
`define SKY130_FD_SC_HD__A211O_4_V
|
|
|
|
/**
|
|
* a211o: 2-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a211o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a211o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a211o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_V
|
|
`define SKY130_FD_SC_HD__A211OI_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, and0_out, B1, C1);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, and0_out, B1, C1);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_1_V
|
|
`define SKY130_FD_SC_HD__A211OI_1_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a211oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a211oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a211oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_2_V
|
|
`define SKY130_FD_SC_HD__A211OI_2_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a211oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a211oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a211oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A211OI_4_V
|
|
`define SKY130_FD_SC_HD__A211OI_4_V
|
|
|
|
/**
|
|
* a211oi: 2-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a211oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a211oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a211oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a211oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A211OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_V
|
|
`define SKY130_FD_SC_HD__A221O_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X , and1_out, and0_out, C1);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X , and1_out, and0_out, C1);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X, and1_out, and0_out, C1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
or or0 (or0_out_X, and1_out, and0_out, C1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_1_V
|
|
`define SKY130_FD_SC_HD__A221O_1_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog wrapper for a221o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a221o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a221o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_2_V
|
|
`define SKY130_FD_SC_HD__A221O_2_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog wrapper for a221o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a221o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a221o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221O_4_V
|
|
`define SKY130_FD_SC_HD__A221O_4_V
|
|
|
|
/**
|
|
* a221o: 2-input AND into first two inputs of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog wrapper for a221o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a221o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a221o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_V
|
|
`define SKY130_FD_SC_HD__A221OI_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , B1, B2 );
|
|
and and1 (and1_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_1_V
|
|
`define SKY130_FD_SC_HD__A221OI_1_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog wrapper for a221oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a221oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a221oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_2_V
|
|
`define SKY130_FD_SC_HD__A221OI_2_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog wrapper for a221oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a221oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a221oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A221OI_4_V
|
|
`define SKY130_FD_SC_HD__A221OI_4_V
|
|
|
|
/**
|
|
* a221oi: 2-input AND into first two inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | C1)
|
|
*
|
|
* Verilog wrapper for a221oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a221oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a221oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a221oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A221OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A222OI_V
|
|
`define SKY130_FD_SC_HD__A222OI_V
|
|
|
|
/**
|
|
* a222oi: 2-input AND into all inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a222oi: 2-input AND into all inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a222oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
C2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input C2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire nand2_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
nand nand2 (nand2_out , C2, C1 );
|
|
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a222oi: 2-input AND into all inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a222oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
C2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input C2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire nand2_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
nand nand2 (nand2_out , C2, C1 );
|
|
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a222oi: 2-input AND into all inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a222oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1,
|
|
C2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
input C2;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire nand2_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
nand nand2 (nand2_out , C2, C1 );
|
|
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a222oi: 2-input AND into all inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a222oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1,
|
|
C2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
input C2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire nand1_out ;
|
|
wire nand2_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2, A1 );
|
|
nand nand1 (nand1_out , B2, B1 );
|
|
nand nand2 (nand2_out , C2, C1 );
|
|
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A222OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A222OI_1_V
|
|
`define SKY130_FD_SC_HD__A222OI_1_V
|
|
|
|
/**
|
|
* a222oi: 2-input AND into all inputs of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
|
|
*
|
|
* Verilog wrapper for a222oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a222oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
C2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input C2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a222oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.C2(C2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a222oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1,
|
|
C2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
input C2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a222oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.C2(C2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A222OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_V
|
|
`define SKY130_FD_SC_HD__A311O_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X , and0_out, C1, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X , and0_out, C1, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X, and0_out, C1, B1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
or or0 (or0_out_X, and0_out, C1, B1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_1_V
|
|
`define SKY130_FD_SC_HD__A311O_1_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a311o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a311o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a311o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_2_V
|
|
`define SKY130_FD_SC_HD__A311O_2_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a311o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a311o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a311o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311O_4_V
|
|
`define SKY130_FD_SC_HD__A311O_4_V
|
|
|
|
/**
|
|
* a311o: 3-input AND into first input of 3-input OR.
|
|
*
|
|
* X = ((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a311o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a311o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a311o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_V
|
|
`define SKY130_FD_SC_HD__A311OI_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y, and0_out, B1, C1);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A3, A1, A2 );
|
|
nor nor0 (nor0_out_Y, and0_out, B1, C1);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_1_V
|
|
`define SKY130_FD_SC_HD__A311OI_1_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a311oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a311oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a311oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_2_V
|
|
`define SKY130_FD_SC_HD__A311OI_2_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a311oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a311oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a311oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A311OI_4_V
|
|
`define SKY130_FD_SC_HD__A311OI_4_V
|
|
|
|
/**
|
|
* a311oi: 3-input AND into first input of 3-input NOR.
|
|
*
|
|
* Y = !((A1 & A2 & A3) | B1 | C1)
|
|
*
|
|
* Verilog wrapper for a311oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a311oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a311oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a311oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A311OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_V
|
|
`define SKY130_FD_SC_HD__A2111O_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X , C1, B1, and0_out, D1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X , C1, B1, and0_out, D1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X, C1, B1, and0_out, D1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
or or0 (or0_out_X, C1, B1, and0_out, D1);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_1_V
|
|
`define SKY130_FD_SC_HD__A2111O_1_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111o with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_2_V
|
|
`define SKY130_FD_SC_HD__A2111O_2_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111o with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111O_4_V
|
|
`define SKY130_FD_SC_HD__A2111O_4_V
|
|
|
|
/**
|
|
* a2111o: 2-input AND into first input of 4-input OR.
|
|
*
|
|
* X = ((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111o with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111o_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111o base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111O_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_V
|
|
`define SKY130_FD_SC_HD__A2111OI_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out , A1, A2 );
|
|
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_0_V
|
|
`define SKY130_FD_SC_HD__A2111OI_0_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111oi with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_0 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_0 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_1_V
|
|
`define SKY130_FD_SC_HD__A2111OI_1_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111oi with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_2_V
|
|
`define SKY130_FD_SC_HD__A2111OI_2_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111oi with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__A2111OI_4_V
|
|
`define SKY130_FD_SC_HD__A2111OI_4_V
|
|
|
|
/**
|
|
* a2111oi: 2-input AND into first input of 4-input NOR.
|
|
*
|
|
* Y = !((A1 & A2) | B1 | C1 | D1)
|
|
*
|
|
* Verilog wrapper for a2111oi with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__a2111oi_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__a2111oi base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__A2111OI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_V
|
|
`define SKY130_FD_SC_HD__AND2_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, A, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, A, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_0_V
|
|
`define SKY130_FD_SC_HD__AND2_0_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog wrapper for and2 with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_0 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_0 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_1_V
|
|
`define SKY130_FD_SC_HD__AND2_1_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog wrapper for and2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_1 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_2_V
|
|
`define SKY130_FD_SC_HD__AND2_2_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog wrapper for and2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2_4_V
|
|
`define SKY130_FD_SC_HD__AND2_4_V
|
|
|
|
/**
|
|
* and2: 2-input AND.
|
|
*
|
|
* Verilog wrapper for and2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2_4 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_V
|
|
`define SKY130_FD_SC_HD__AND2B_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X , not0_out, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X , not0_out, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b (
|
|
X ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X, not0_out, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b (
|
|
X ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X, not0_out, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_1_V
|
|
`define SKY130_FD_SC_HD__AND2B_1_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and2b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b_1 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b_1 (
|
|
X ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_2_V
|
|
`define SKY130_FD_SC_HD__AND2B_2_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and2b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b_2 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b_2 (
|
|
X ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND2B_4_V
|
|
`define SKY130_FD_SC_HD__AND2B_4_V
|
|
|
|
/**
|
|
* and2b: 2-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and2b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b_4 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and2b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and2b_4 (
|
|
X ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and2b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND2B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_V
|
|
`define SKY130_FD_SC_HD__AND3_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X , C, A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X , C, A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, C, A, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, C, A, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_1_V
|
|
`define SKY130_FD_SC_HD__AND3_1_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog wrapper for and3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_2_V
|
|
`define SKY130_FD_SC_HD__AND3_2_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog wrapper for and3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3_4_V
|
|
`define SKY130_FD_SC_HD__AND3_4_V
|
|
|
|
/**
|
|
* and3: 3-input AND.
|
|
*
|
|
* Verilog wrapper for and3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_V
|
|
`define SKY130_FD_SC_HD__AND3B_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X , C, not0_out, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X , C, not0_out, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X, C, not0_out, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X, C, not0_out, B );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_1_V
|
|
`define SKY130_FD_SC_HD__AND3B_1_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and3b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b_1 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and3b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b_1 (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and3b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_2_V
|
|
`define SKY130_FD_SC_HD__AND3B_2_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and3b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b_2 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and3b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b_2 (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and3b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND3B_4_V
|
|
`define SKY130_FD_SC_HD__AND3B_4_V
|
|
|
|
/**
|
|
* and3b: 3-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and3b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b_4 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and3b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and3b_4 (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and3b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND3B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_V
|
|
`define SKY130_FD_SC_HD__AND4_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X , A, B, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X , A, B, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, A, B, C, D );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, A, B, C, D );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_1_V
|
|
`define SKY130_FD_SC_HD__AND4_1_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog wrapper for and4 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_2_V
|
|
`define SKY130_FD_SC_HD__AND4_2_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog wrapper for and4 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4_4_V
|
|
`define SKY130_FD_SC_HD__AND4_4_V
|
|
|
|
/**
|
|
* and4: 4-input AND.
|
|
*
|
|
* Verilog wrapper for and4 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_V
|
|
`define SKY130_FD_SC_HD__AND4B_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X , not0_out, B, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X , not0_out, B, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X, not0_out, B, C, D);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
and and0 (and0_out_X, not0_out, B, C, D);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_1_V
|
|
`define SKY130_FD_SC_HD__AND4B_1_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and4b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b_1 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b_1 (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_2_V
|
|
`define SKY130_FD_SC_HD__AND4B_2_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and4b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b_2 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b_2 (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4B_4_V
|
|
`define SKY130_FD_SC_HD__AND4B_4_V
|
|
|
|
/**
|
|
* and4b: 4-input AND, first input inverted.
|
|
*
|
|
* Verilog wrapper for and4b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b_4 (
|
|
X ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4b_4 (
|
|
X ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4b base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_V
|
|
`define SKY130_FD_SC_HD__AND4BB_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb (
|
|
X ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A_N, B_N );
|
|
and and0 (and0_out_X , nor0_out, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb (
|
|
X ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A_N, B_N );
|
|
and and0 (and0_out_X , nor0_out, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb (
|
|
X ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A_N, B_N );
|
|
and and0 (and0_out_X, nor0_out, C, D );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb (
|
|
X ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A_N, B_N );
|
|
and and0 (and0_out_X, nor0_out, C, D );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_1_V
|
|
`define SKY130_FD_SC_HD__AND4BB_1_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for and4bb with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb_1 (
|
|
X ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4bb base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb_1 (
|
|
X ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4bb base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_2_V
|
|
`define SKY130_FD_SC_HD__AND4BB_2_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for and4bb with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb_2 (
|
|
X ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4bb base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb_2 (
|
|
X ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4bb base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__AND4BB_4_V
|
|
`define SKY130_FD_SC_HD__AND4BB_4_V
|
|
|
|
/**
|
|
* and4bb: 4-input AND, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for and4bb with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb_4 (
|
|
X ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__and4bb base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__and4bb_4 (
|
|
X ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output X ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__and4bb base (
|
|
.X(X),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__AND4BB_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_V
|
|
`define SKY130_FD_SC_HD__BUF_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_1_V
|
|
`define SKY130_FD_SC_HD__BUF_1_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_2_V
|
|
`define SKY130_FD_SC_HD__BUF_2_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_4_V
|
|
`define SKY130_FD_SC_HD__BUF_4_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_4 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_4 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_6_V
|
|
`define SKY130_FD_SC_HD__BUF_6_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 6 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_6 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_6 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_6_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_8_V
|
|
`define SKY130_FD_SC_HD__BUF_8_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_8 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_8 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_12_V
|
|
`define SKY130_FD_SC_HD__BUF_12_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 12 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_12 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_12 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_12_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUF_16_V
|
|
`define SKY130_FD_SC_HD__BUF_16_V
|
|
|
|
/**
|
|
* buf: Buffer.
|
|
*
|
|
* Verilog wrapper for buf with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_16 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__buf_16 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__buf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUF_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_8_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_8_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog wrapper for bufbuf with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf_8 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__bufbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf_8 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__bufbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFBUF_16_V
|
|
`define SKY130_FD_SC_HD__BUFBUF_16_V
|
|
|
|
/**
|
|
* bufbuf: Double buffer.
|
|
*
|
|
* Verilog wrapper for bufbuf with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf_16 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__bufbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufbuf_16 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__bufbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFBUF_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_V
|
|
`define SKY130_FD_SC_HD__BUFINV_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_8_V
|
|
`define SKY130_FD_SC_HD__BUFINV_8_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog wrapper for bufinv with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv_8 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__bufinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv_8 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__bufinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__BUFINV_16_V
|
|
`define SKY130_FD_SC_HD__BUFINV_16_V
|
|
|
|
/**
|
|
* bufinv: Buffer followed by inverter.
|
|
*
|
|
* Verilog wrapper for bufinv with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv_16 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__bufinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__bufinv_16 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__bufinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__BUFINV_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_1_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_1_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog wrapper for clkbuf with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_2_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_2_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog wrapper for clkbuf with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_4_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_4_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog wrapper for clkbuf with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_4 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_4 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_8_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_8_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog wrapper for clkbuf with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_8 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_8 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKBUF_16_V
|
|
`define SKY130_FD_SC_HD__CLKBUF_16_V
|
|
|
|
/**
|
|
* clkbuf: Clock tree buffer.
|
|
*
|
|
* Verilog wrapper for clkbuf with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_16 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkbuf_16 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkbuf base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKBUF_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s15 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s15 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s15 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
|
|
|
|
/**
|
|
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s15 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15_2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s15 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s15_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s15 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s18 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s18 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s18 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
|
|
|
|
/**
|
|
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s18 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18_2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s18 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s18_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s18 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s25 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s25 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s25 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
|
|
|
|
/**
|
|
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s25 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25_2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s25 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s25_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s25 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s50 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s50 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s50 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
|
|
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
|
|
|
|
/**
|
|
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
|
|
* gates.
|
|
*
|
|
* Verilog wrapper for clkdlybuf4s50 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50_2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkdlybuf4s50 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkdlybuf4s50_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkdlybuf4s50 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_V
|
|
`define SKY130_FD_SC_HD__CLKINV_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_1_V
|
|
`define SKY130_FD_SC_HD__CLKINV_1_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinv with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_1 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_1 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_2_V
|
|
`define SKY130_FD_SC_HD__CLKINV_2_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinv with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_2 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_2 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_4_V
|
|
`define SKY130_FD_SC_HD__CLKINV_4_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinv with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_4 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_4 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_8_V
|
|
`define SKY130_FD_SC_HD__CLKINV_8_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinv with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_8 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_8 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINV_16_V
|
|
`define SKY130_FD_SC_HD__CLKINV_16_V
|
|
|
|
/**
|
|
* clkinv: Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinv with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_16 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinv_16 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINV_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_2_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_2_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinvlp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp_2 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinvlp base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp_2 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinvlp base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CLKINVLP_4_V
|
|
`define SKY130_FD_SC_HD__CLKINVLP_4_V
|
|
|
|
/**
|
|
* clkinvlp: Lower power Clock tree inverter.
|
|
*
|
|
* Verilog wrapper for clkinvlp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp_4 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__clkinvlp base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__clkinvlp_4 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__clkinvlp base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CLKINVLP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CONB_V
|
|
`define SKY130_FD_SC_HD__CONB_V
|
|
|
|
/**
|
|
* conb: Constant value, low, high outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* conb: Constant value, low, high outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__conb (
|
|
HI ,
|
|
LO ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output HI ;
|
|
output LO ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pullup0_out_HI ;
|
|
wire pulldown0_out_LO;
|
|
|
|
// Name Output Other arguments
|
|
pullup pullup0 (pullup0_out_HI );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
|
|
pulldown pulldown0 (pulldown0_out_LO);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* conb: Constant value, low, high outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__conb (
|
|
HI ,
|
|
LO ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output HI ;
|
|
output LO ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pullup0_out_HI ;
|
|
wire pulldown0_out_LO;
|
|
|
|
// Name Output Other arguments
|
|
pullup pullup0 (pullup0_out_HI );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
|
|
pulldown pulldown0 (pulldown0_out_LO);
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CONB_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
|
|
|
|
/**
|
|
* conb: Constant value, low, high outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__conb (
|
|
HI,
|
|
LO
|
|
);
|
|
|
|
// Module ports
|
|
output HI;
|
|
output LO;
|
|
|
|
// Name Output
|
|
pullup pullup0 (HI );
|
|
pulldown pulldown0 (LO );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CONB_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
|
|
|
|
/**
|
|
* conb: Constant value, low, high outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__conb (
|
|
HI,
|
|
LO
|
|
);
|
|
|
|
// Module ports
|
|
output HI;
|
|
output LO;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output
|
|
pullup pullup0 (HI );
|
|
pulldown pulldown0 (LO );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CONB_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__CONB_1_V
|
|
`define SKY130_FD_SC_HD__CONB_1_V
|
|
|
|
/**
|
|
* conb: Constant value, low, high outputs.
|
|
*
|
|
* Verilog wrapper for conb with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__conb_1 (
|
|
HI ,
|
|
LO ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output HI ;
|
|
output LO ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__conb base (
|
|
.HI(HI),
|
|
.LO(LO),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__conb_1 (
|
|
HI,
|
|
LO
|
|
);
|
|
|
|
output HI;
|
|
output LO;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__conb base (
|
|
.HI(HI),
|
|
.LO(LO)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__CONB_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_V
|
|
`define SKY130_FD_SC_HD__DECAP_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap ();
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_3_V
|
|
`define SKY130_FD_SC_HD__DECAP_3_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog wrapper for decap with size of 3 units (invalid?).
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_3 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__decap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_3 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__decap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_4_V
|
|
`define SKY130_FD_SC_HD__DECAP_4_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog wrapper for decap with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_4 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__decap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_4 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__decap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_6_V
|
|
`define SKY130_FD_SC_HD__DECAP_6_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog wrapper for decap with size of 6 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_6 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__decap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_6 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__decap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_6_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_8_V
|
|
`define SKY130_FD_SC_HD__DECAP_8_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog wrapper for decap with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_8 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__decap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_8 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__decap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DECAP_12_V
|
|
`define SKY130_FD_SC_HD__DECAP_12_V
|
|
|
|
/**
|
|
* decap: Decoupling capacitance filler.
|
|
*
|
|
* Verilog wrapper for decap with size of 12 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_12 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__decap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__decap_12 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__decap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DECAP_12_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_V
|
|
`define SKY130_FD_SC_HD__DFBBN_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
not not2 (CLK , CLK_N );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q ;
|
|
wire CLK_N_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire SET_B_delayed ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
not not2 (CLK , CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
not not2 (CLK , CLK_N );
|
|
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q ;
|
|
wire CLK_N_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire SET_B_delayed ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
not not2 (CLK , CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_1_V
|
|
`define SKY130_FD_SC_HD__DFBBN_1_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfbbn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBN_2_V
|
|
`define SKY130_FD_SC_HD__DFBBN_2_V
|
|
|
|
/**
|
|
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfbbn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBP_V
|
|
`define SKY130_FD_SC_HD__DFBBP_V
|
|
|
|
/**
|
|
* dfbbp: Delay flop, inverted set, inverted reset,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfbbp: Delay flop, inverted set, inverted reset,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire SET ;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfbbp: Delay flop, inverted set, inverted reset,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire buf_Q ;
|
|
wire CLK_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire SET_B_delayed ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfbbp: Delay flop, inverted set, inverted reset,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire SET ;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfbbp: Delay flop, inverted set, inverted reset,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire buf_Q ;
|
|
wire CLK_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire SET_B_delayed ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFBBP_1_V
|
|
`define SKY130_FD_SC_HD__DFBBP_1_V
|
|
|
|
/**
|
|
* dfbbp: Delay flop, inverted set, inverted reset,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfbbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfbbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.CLK(CLK),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfbbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfbbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.CLK(CLK),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFBBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_V
|
|
`define SKY130_FD_SC_HD__DFRBP_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire RESET;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire RESET;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_1_V
|
|
`define SKY130_FD_SC_HD__DFRBP_1_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfrbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRBP_2_V
|
|
`define SKY130_FD_SC_HD__DFRBP_2_V
|
|
|
|
/**
|
|
* dfrbp: Delay flop, inverted reset, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfrbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTN_V
|
|
`define SKY130_FD_SC_HD__DFRTN_V
|
|
|
|
/**
|
|
* dfrtn: Delay flop, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfrtn: Delay flop, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intclk, CLK_N );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfrtn: Delay flop, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_N_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intclk, CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfrtn: Delay flop, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intclk, CLK_N );
|
|
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfrtn: Delay flop, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_N_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intclk, CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTN_1_V
|
|
`define SKY130_FD_SC_HD__DFRTN_1_V
|
|
|
|
/**
|
|
* dfrtn: Delay flop, inverted reset, inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfrtn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtn_1 (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfrtn base (
|
|
.Q(Q),
|
|
.CLK_N(CLK_N),
|
|
.D(D),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtn_1 (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfrtn base (
|
|
.Q(Q),
|
|
.CLK_N(CLK_N),
|
|
.D(D),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_V
|
|
`define SKY130_FD_SC_HD__DFRTP_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire RESET;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire RESET;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_1_V
|
|
`define SKY130_FD_SC_HD__DFRTP_1_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog wrapper for dfrtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_2_V
|
|
`define SKY130_FD_SC_HD__DFRTP_2_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog wrapper for dfrtp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFRTP_4_V
|
|
`define SKY130_FD_SC_HD__DFRTP_4_V
|
|
|
|
/**
|
|
* dfrtp: Delay flop, inverted reset, single output.
|
|
*
|
|
* Verilog wrapper for dfrtp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfrtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFRTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_V
|
|
`define SKY130_FD_SC_HD__DFSBP_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire SET ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( SET_B_delayed === 1'b1 );
|
|
assign cond1 = ( SET_B === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire SET ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( SET_B_delayed === 1'b1 );
|
|
assign cond1 = ( SET_B === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_1_V
|
|
`define SKY130_FD_SC_HD__DFSBP_1_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfsbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSBP_2_V
|
|
`define SKY130_FD_SC_HD__DFSBP_2_V
|
|
|
|
/**
|
|
* dfsbp: Delay flop, inverted set, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfsbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfsbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_V
|
|
`define SKY130_FD_SC_HD__DFSTP_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire SET ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( SET_B_delayed === 1'b1 );
|
|
assign cond1 = ( SET_B === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
wire SET ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( SET_B_delayed === 1'b1 );
|
|
assign cond1 = ( SET_B === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_1_V
|
|
`define SKY130_FD_SC_HD__DFSTP_1_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog wrapper for dfstp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_2_V
|
|
`define SKY130_FD_SC_HD__DFSTP_2_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog wrapper for dfstp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFSTP_4_V
|
|
`define SKY130_FD_SC_HD__DFSTP_4_V
|
|
|
|
/**
|
|
* dfstp: Delay flop, inverted set, single output.
|
|
*
|
|
* Verilog wrapper for dfstp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfstp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFSTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_V
|
|
`define SKY130_FD_SC_HD__DFXBP_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_1_V
|
|
`define SKY130_FD_SC_HD__DFXBP_1_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfxbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp_1 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXBP_2_V
|
|
`define SKY130_FD_SC_HD__DFXBP_2_V
|
|
|
|
/**
|
|
* dfxbp: Delay flop, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dfxbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxbp_2 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_V
|
|
`define SKY130_FD_SC_HD__DFXTP_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp (
|
|
Q ,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp (
|
|
Q ,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_1_V
|
|
`define SKY130_FD_SC_HD__DFXTP_1_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog wrapper for dfxtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp_1 (
|
|
Q ,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_2_V
|
|
`define SKY130_FD_SC_HD__DFXTP_2_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog wrapper for dfxtp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp_2 (
|
|
Q ,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DFXTP_4_V
|
|
`define SKY130_FD_SC_HD__DFXTP_4_V
|
|
|
|
/**
|
|
* dfxtp: Delay flop, single output.
|
|
*
|
|
* Verilog wrapper for dfxtp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dfxtp_4 (
|
|
Q ,
|
|
CLK,
|
|
D
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DFXTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DIODE_V
|
|
`define SKY130_FD_SC_HD__DIODE_V
|
|
|
|
/**
|
|
* diode: Antenna tie-down diode.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* diode: Antenna tie-down diode.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__diode (
|
|
DIODE,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input DIODE;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* diode: Antenna tie-down diode.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__diode (
|
|
DIODE,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input DIODE;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
|
|
|
|
/**
|
|
* diode: Antenna tie-down diode.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__diode (
|
|
DIODE
|
|
);
|
|
|
|
// Module ports
|
|
input DIODE;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
|
|
|
|
/**
|
|
* diode: Antenna tie-down diode.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__diode (
|
|
DIODE
|
|
);
|
|
|
|
// Module ports
|
|
input DIODE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DIODE_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DIODE_2_V
|
|
`define SKY130_FD_SC_HD__DIODE_2_V
|
|
|
|
/**
|
|
* diode: Antenna tie-down diode.
|
|
*
|
|
* Verilog wrapper for diode with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__diode_2 (
|
|
DIODE,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input DIODE;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__diode base (
|
|
.DIODE(DIODE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__diode_2 (
|
|
DIODE
|
|
);
|
|
|
|
input DIODE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__diode base (
|
|
.DIODE(DIODE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DIODE_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp (
|
|
GCLK,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire clkn;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (clkn , CLK );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
|
|
and and0 (GCLK , m0, CLK );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp (
|
|
GCLK,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire clkn ;
|
|
wire CLK_delayed ;
|
|
wire GATE_delayed;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (clkn , CLK_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
|
|
and and0 (GCLK , m0, CLK_delayed );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp (
|
|
GCLK,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire clkn;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (clkn , CLK );
|
|
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
|
|
and and0 (GCLK , m0, CLK );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp (
|
|
GCLK,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire clkn ;
|
|
wire CLK_delayed ;
|
|
wire GATE_delayed;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (clkn , CLK_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
|
|
and and0 (GCLK , m0, CLK_delayed );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_1_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_1_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog wrapper for dlclkp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp_1 (
|
|
GCLK,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlclkp base (
|
|
.GCLK(GCLK),
|
|
.GATE(GATE),
|
|
.CLK(CLK),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp_1 (
|
|
GCLK,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlclkp base (
|
|
.GCLK(GCLK),
|
|
.GATE(GATE),
|
|
.CLK(CLK)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_2_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_2_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog wrapper for dlclkp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp_2 (
|
|
GCLK,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlclkp base (
|
|
.GCLK(GCLK),
|
|
.GATE(GATE),
|
|
.CLK(CLK),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp_2 (
|
|
GCLK,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlclkp base (
|
|
.GCLK(GCLK),
|
|
.GATE(GATE),
|
|
.CLK(CLK)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLCLKP_4_V
|
|
`define SKY130_FD_SC_HD__DLCLKP_4_V
|
|
|
|
/**
|
|
* dlclkp: Clock gate.
|
|
*
|
|
* Verilog wrapper for dlclkp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp_4 (
|
|
GCLK,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlclkp base (
|
|
.GCLK(GCLK),
|
|
.GATE(GATE),
|
|
.CLK(CLK),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlclkp_4 (
|
|
GCLK,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
output GCLK;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlclkp base (
|
|
.GCLK(GCLK),
|
|
.GATE(GATE),
|
|
.CLK(CLK)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLCLKP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_V
|
|
`define SKY130_FD_SC_HD__DLRBN_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate;
|
|
wire buf_Q ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intgate, GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_N_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intgate, GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate;
|
|
wire buf_Q ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intgate, GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_N_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intgate, GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_1_V
|
|
`define SKY130_FD_SC_HD__DLRBN_1_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlrbn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBN_2_V
|
|
`define SKY130_FD_SC_HD__DLRBN_2_V
|
|
|
|
/**
|
|
* dlrbn: Delay latch, inverted reset, inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlrbn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_V
|
|
`define SKY130_FD_SC_HD__DLRBP_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_1_V
|
|
`define SKY130_FD_SC_HD__DLRBP_1_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlrbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRBP_2_V
|
|
`define SKY130_FD_SC_HD__DLRBP_2_V
|
|
|
|
/**
|
|
* dlrbp: Delay latch, inverted reset, non-inverted enable,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlrbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_V
|
|
`define SKY130_FD_SC_HD__DLRTN_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate;
|
|
wire buf_Q ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intgate, GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_N_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intgate, GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate;
|
|
wire buf_Q ;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intgate, GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire intgate ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_N_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intgate, GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_1_V
|
|
`define SKY130_FD_SC_HD__DLRTN_1_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlrtn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn_1 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrtn base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn_1 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrtn base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_2_V
|
|
`define SKY130_FD_SC_HD__DLRTN_2_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlrtn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn_2 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrtn base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn_2 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrtn base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTN_4_V
|
|
`define SKY130_FD_SC_HD__DLRTN_4_V
|
|
|
|
/**
|
|
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlrtn with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn_4 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrtn base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtn_4 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE_N ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrtn base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTN_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_V
|
|
`define SKY130_FD_SC_HD__DLRTP_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Local signals
|
|
wire RESET;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire GATE_delayed ;
|
|
wire RESET_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire buf_Q ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_1_V
|
|
`define SKY130_FD_SC_HD__DLRTP_1_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for dlrtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp_1 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrtp base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp_1 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrtp base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_2_V
|
|
`define SKY130_FD_SC_HD__DLRTP_2_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for dlrtp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp_2 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrtp base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp_2 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrtp base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLRTP_4_V
|
|
`define SKY130_FD_SC_HD__DLRTP_4_V
|
|
|
|
/**
|
|
* dlrtp: Delay latch, inverted reset, non-inverted enable,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for dlrtp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp_4 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlrtp base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlrtp_4 (
|
|
Q ,
|
|
RESET_B,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
input RESET_B;
|
|
input D ;
|
|
input GATE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlrtp base (
|
|
.Q(Q),
|
|
.RESET_B(RESET_B),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLRTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_V
|
|
`define SKY130_FD_SC_HD__DLXBN_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (GATE , GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q ;
|
|
wire GATE_N_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (GATE , GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (GATE , GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q ;
|
|
wire GATE_N_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (GATE , GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1 );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_1_V
|
|
`define SKY130_FD_SC_HD__DLXBN_1_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlxbn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBN_2_V
|
|
`define SKY130_FD_SC_HD__DLXBN_2_V
|
|
|
|
/**
|
|
* dlxbn: Delay latch, inverted enable, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlxbn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBP_V
|
|
`define SKY130_FD_SC_HD__DLXBP_V
|
|
|
|
/**
|
|
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire GATE_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire GATE_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXBP_1_V
|
|
`define SKY130_FD_SC_HD__DLXBP_1_V
|
|
|
|
/**
|
|
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
|
|
*
|
|
* Verilog wrapper for dlxbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input GATE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_V
|
|
`define SKY130_FD_SC_HD__DLXTN_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn (
|
|
Q ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (GATE , GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn (
|
|
Q ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q ;
|
|
wire GATE_N_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (GATE , GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn (
|
|
Q ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (GATE , GATE_N );
|
|
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn (
|
|
Q ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire GATE ;
|
|
wire buf_Q ;
|
|
wire GATE_N_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (GATE , GATE_N_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_1_V
|
|
`define SKY130_FD_SC_HD__DLXTN_1_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlxtn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn_1 (
|
|
Q ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxtn base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn_1 (
|
|
Q ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxtn base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_2_V
|
|
`define SKY130_FD_SC_HD__DLXTN_2_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlxtn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn_2 (
|
|
Q ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxtn base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn_2 (
|
|
Q ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxtn base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTN_4_V
|
|
`define SKY130_FD_SC_HD__DLXTN_4_V
|
|
|
|
/**
|
|
* dlxtn: Delay latch, inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlxtn with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn_4 (
|
|
Q ,
|
|
D ,
|
|
GATE_N,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxtn base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE_N(GATE_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtn_4 (
|
|
Q ,
|
|
D ,
|
|
GATE_N
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxtn base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE_N(GATE_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTN_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTP_V
|
|
`define SKY130_FD_SC_HD__DLXTP_V
|
|
|
|
/**
|
|
* dlxtp: Delay latch, non-inverted enable, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlxtp: Delay latch, non-inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtp (
|
|
Q ,
|
|
D ,
|
|
GATE,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlxtp: Delay latch, non-inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtp (
|
|
Q ,
|
|
D ,
|
|
GATE,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire GATE_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlxtp: Delay latch, non-inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtp (
|
|
Q ,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlxtp: Delay latch, non-inverted enable, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtp (
|
|
Q ,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input GATE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire GATE_delayed;
|
|
wire D_delayed ;
|
|
reg notifier ;
|
|
wire awake ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLXTP_1_V
|
|
`define SKY130_FD_SC_HD__DLXTP_1_V
|
|
|
|
/**
|
|
* dlxtp: Delay latch, non-inverted enable, single output.
|
|
*
|
|
* Verilog wrapper for dlxtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtp_1 (
|
|
Q ,
|
|
D ,
|
|
GATE,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlxtp base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE(GATE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlxtp_1 (
|
|
Q ,
|
|
D ,
|
|
GATE
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input GATE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlxtp base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.GATE(GATE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLXTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD1_V
|
|
|
|
/**
|
|
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_1_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD1_1_V
|
|
|
|
/**
|
|
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
|
|
*
|
|
* Verilog wrapper for dlygate4sd1 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd1_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlygate4sd1 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd1_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlygate4sd1 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD2_V
|
|
|
|
/**
|
|
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd2 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_1_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD2_1_V
|
|
|
|
/**
|
|
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
|
|
*
|
|
* Verilog wrapper for dlygate4sd2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd2_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlygate4sd2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd2_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlygate4sd2 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD3_V
|
|
|
|
/**
|
|
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd3 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd3 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd3 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd3 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_1_V
|
|
`define SKY130_FD_SC_HD__DLYGATE4SD3_1_V
|
|
|
|
/**
|
|
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
|
|
*
|
|
* Verilog wrapper for dlygate4sd3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd3_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlygate4sd3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlygate4sd3_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlygate4sd3 base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S2S_V
|
|
|
|
/**
|
|
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
|
|
* horizontal route.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s2s (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s2s (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s2s (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s2s (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
|
|
|
|
/**
|
|
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
|
|
* horizontal route.
|
|
*
|
|
* Verilog wrapper for dlymetal6s2s with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s2s_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlymetal6s2s base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s2s_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlymetal6s2s base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S4S_V
|
|
|
|
/**
|
|
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s4s (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s4s (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s4s (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s4s (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
|
|
|
|
/**
|
|
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog wrapper for dlymetal6s4s with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s4s_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlymetal6s4s base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s4s_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlymetal6s4s base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S6S_V
|
|
|
|
/**
|
|
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s6s (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s6s (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
|
|
|
|
/**
|
|
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s6s (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
|
|
|
|
/**
|
|
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s6s (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
|
|
`define SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
|
|
|
|
/**
|
|
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
|
|
* horizontal route.
|
|
*
|
|
* Verilog wrapper for dlymetal6s6s with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s6s_1 (
|
|
X ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__dlymetal6s6s base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__dlymetal6s6s_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__dlymetal6s6s base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_V
|
|
`define SKY130_FD_SC_HD__EBUFN_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood_pp0_out_A ;
|
|
wire pwrgood_pp1_out_teb;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
|
|
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood_pp0_out_A ;
|
|
wire pwrgood_pp1_out_teb;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
|
|
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Name Output Other arguments
|
|
bufif0 bufif00 (Z , A, TE_B );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output Other arguments
|
|
bufif0 bufif00 (Z , A, TE_B );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_1_V
|
|
`define SKY130_FD_SC_HD__EBUFN_1_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog wrapper for ebufn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_1 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_1 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_2_V
|
|
`define SKY130_FD_SC_HD__EBUFN_2_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog wrapper for ebufn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_2 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_2 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_4_V
|
|
`define SKY130_FD_SC_HD__EBUFN_4_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog wrapper for ebufn with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_4 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_4 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EBUFN_8_V
|
|
`define SKY130_FD_SC_HD__EBUFN_8_V
|
|
|
|
/**
|
|
* ebufn: Tri-state buffer, negative enable.
|
|
*
|
|
* Verilog wrapper for ebufn with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_8 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ebufn_8 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ebufn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EBUFN_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXBP_V
|
|
`define SKY130_FD_SC_HD__EDFXBP_V
|
|
|
|
/**
|
|
* edfxbp: Delay flop with loopback enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* edfxbp: Delay flop with loopback enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* edfxbp: Delay flop with loopback enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* edfxbp: Delay flop with loopback enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* edfxbp: Delay flop with loopback enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXBP_1_V
|
|
`define SKY130_FD_SC_HD__EDFXBP_1_V
|
|
|
|
/**
|
|
* edfxbp: Delay flop with loopback enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for edfxbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__edfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxbp_1 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__edfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXTP_V
|
|
`define SKY130_FD_SC_HD__EDFXTP_V
|
|
|
|
/**
|
|
* edfxtp: Delay flop with loopback enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* edfxtp: Delay flop with loopback enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* edfxtp: Delay flop with loopback enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* edfxtp: Delay flop with loopback enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxtp (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* edfxtp: Delay flop with loopback enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxtp (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EDFXTP_1_V
|
|
`define SKY130_FD_SC_HD__EDFXTP_1_V
|
|
|
|
/**
|
|
* edfxtp: Delay flop with loopback enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for edfxtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__edfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__edfxtp_1 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__edfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EDFXTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_V
|
|
`define SKY130_FD_SC_HD__EINVN_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood_pp0_out_A ;
|
|
wire pwrgood_pp1_out_teb;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
|
|
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood_pp0_out_A ;
|
|
wire pwrgood_pp1_out_teb;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
|
|
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Name Output Other arguments
|
|
notif0 notif00 (Z , A, TE_B );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output Other arguments
|
|
notif0 notif00 (Z , A, TE_B );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_0_V
|
|
`define SKY130_FD_SC_HD__EINVN_0_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog wrapper for einvn with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_0 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_0 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_1_V
|
|
`define SKY130_FD_SC_HD__EINVN_1_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog wrapper for einvn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_1 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_1 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_2_V
|
|
`define SKY130_FD_SC_HD__EINVN_2_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog wrapper for einvn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_2 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_2 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_4_V
|
|
`define SKY130_FD_SC_HD__EINVN_4_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog wrapper for einvn with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_4 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_4 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVN_8_V
|
|
`define SKY130_FD_SC_HD__EINVN_8_V
|
|
|
|
/**
|
|
* einvn: Tri-state inverter, negative enable.
|
|
*
|
|
* Verilog wrapper for einvn with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_8 (
|
|
Z ,
|
|
A ,
|
|
TE_B,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvn_8 (
|
|
Z ,
|
|
A ,
|
|
TE_B
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvn base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE_B(TE_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVN_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_V
|
|
`define SKY130_FD_SC_HD__EINVP_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp (
|
|
Z ,
|
|
A ,
|
|
TE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood_pp0_out_A ;
|
|
wire pwrgood_pp1_out_TE;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
|
|
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp (
|
|
Z ,
|
|
A ,
|
|
TE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood_pp0_out_A ;
|
|
wire pwrgood_pp1_out_TE;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
|
|
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp (
|
|
Z ,
|
|
A ,
|
|
TE
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE;
|
|
|
|
// Name Output Other arguments
|
|
notif1 notif10 (Z , A, TE );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp (
|
|
Z ,
|
|
A ,
|
|
TE
|
|
);
|
|
|
|
// Module ports
|
|
output Z ;
|
|
input A ;
|
|
input TE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output Other arguments
|
|
notif1 notif10 (Z , A, TE );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_1_V
|
|
`define SKY130_FD_SC_HD__EINVP_1_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog wrapper for einvp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_1 (
|
|
Z ,
|
|
A ,
|
|
TE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_1 (
|
|
Z ,
|
|
A ,
|
|
TE
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_2_V
|
|
`define SKY130_FD_SC_HD__EINVP_2_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog wrapper for einvp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_2 (
|
|
Z ,
|
|
A ,
|
|
TE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_2 (
|
|
Z ,
|
|
A ,
|
|
TE
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_4_V
|
|
`define SKY130_FD_SC_HD__EINVP_4_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog wrapper for einvp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_4 (
|
|
Z ,
|
|
A ,
|
|
TE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_4 (
|
|
Z ,
|
|
A ,
|
|
TE
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__EINVP_8_V
|
|
`define SKY130_FD_SC_HD__EINVP_8_V
|
|
|
|
/**
|
|
* einvp: Tri-state inverter, positive enable.
|
|
*
|
|
* Verilog wrapper for einvp with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_8 (
|
|
Z ,
|
|
A ,
|
|
TE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__einvp_8 (
|
|
Z ,
|
|
A ,
|
|
TE
|
|
);
|
|
|
|
output Z ;
|
|
input A ;
|
|
input TE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__einvp base (
|
|
.Z(Z),
|
|
.A(A),
|
|
.TE(TE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__EINVP_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_V
|
|
`define SKY130_FD_SC_HD__FA_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire and2_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or1_out_COUT ;
|
|
wire pwrgood_pp0_out_COUT;
|
|
wire or2_out_SUM ;
|
|
wire pwrgood_pp1_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , CIN, B );
|
|
and and0 (and0_out , or0_out, A );
|
|
and and1 (and1_out , B, CIN );
|
|
or or1 (or1_out_COUT , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
|
|
buf buf0 (COUT , pwrgood_pp0_out_COUT );
|
|
and and2 (and2_out , CIN, A, B );
|
|
nor nor0 (nor0_out , A, or0_out );
|
|
nor nor1 (nor1_out , nor0_out, COUT );
|
|
or or2 (or2_out_SUM , nor1_out, and2_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
|
|
buf buf1 (SUM , pwrgood_pp1_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire and2_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or1_out_COUT ;
|
|
wire pwrgood_pp0_out_COUT;
|
|
wire or2_out_SUM ;
|
|
wire pwrgood_pp1_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , CIN, B );
|
|
and and0 (and0_out , or0_out, A );
|
|
and and1 (and1_out , B, CIN );
|
|
or or1 (or1_out_COUT , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
|
|
buf buf0 (COUT , pwrgood_pp0_out_COUT );
|
|
and and2 (and2_out , CIN, A, B );
|
|
nor nor0 (nor0_out , A, or0_out );
|
|
nor nor1 (nor1_out , nor0_out, COUT );
|
|
or or2 (or2_out_SUM , nor1_out, and2_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
|
|
buf buf1 (SUM , pwrgood_pp1_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__FA_FUNCTIONAL_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire and2_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or1_out_COUT;
|
|
wire or2_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , CIN, B );
|
|
and and0 (and0_out , or0_out, A );
|
|
and and1 (and1_out , B, CIN );
|
|
or or1 (or1_out_COUT, and1_out, and0_out);
|
|
buf buf0 (COUT , or1_out_COUT );
|
|
and and2 (and2_out , CIN, A, B );
|
|
nor nor0 (nor0_out , A, or0_out );
|
|
nor nor1 (nor1_out , nor0_out, COUT );
|
|
or or2 (or2_out_SUM , nor1_out, and2_out);
|
|
buf buf1 (SUM , or2_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__FA_BEHAVIORAL_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire and2_out ;
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or1_out_COUT;
|
|
wire or2_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , CIN, B );
|
|
and and0 (and0_out , or0_out, A );
|
|
and and1 (and1_out , B, CIN );
|
|
or or1 (or1_out_COUT, and1_out, and0_out);
|
|
buf buf0 (COUT , or1_out_COUT );
|
|
and and2 (and2_out , CIN, A, B );
|
|
nor nor0 (nor0_out , A, or0_out );
|
|
nor nor1 (nor1_out , nor0_out, COUT );
|
|
or or2 (or2_out_SUM , nor1_out, and2_out);
|
|
buf buf1 (SUM , or2_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_1_V
|
|
`define SKY130_FD_SC_HD__FA_1_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog wrapper for fa with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fa base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fa base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_2_V
|
|
`define SKY130_FD_SC_HD__FA_2_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog wrapper for fa with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa_2 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fa base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa_2 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fa base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FA_4_V
|
|
`define SKY130_FD_SC_HD__FA_4_V
|
|
|
|
/**
|
|
* fa: Full adder.
|
|
*
|
|
* Verilog wrapper for fa with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa_4 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fa base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fa_4 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fa base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FA_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAH_V
|
|
`define SKY130_FD_SC_HD__FAH_V
|
|
|
|
/**
|
|
* fah: Full adder.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* fah: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fah (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT ;
|
|
wire pwrgood_pp1_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM , A, B, CI );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
|
|
buf buf0 (SUM , pwrgood_pp0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, CI );
|
|
and and2 (b_ci , B, CI );
|
|
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
|
|
buf buf1 (COUT , pwrgood_pp1_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* fah: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fah (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT ;
|
|
wire pwrgood_pp1_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM , A, B, CI );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
|
|
buf buf0 (SUM , pwrgood_pp0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, CI );
|
|
and and2 (b_ci , B, CI );
|
|
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
|
|
buf buf1 (COUT , pwrgood_pp1_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAH_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
|
|
|
|
/**
|
|
* fah: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fah (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM, A, B, CI );
|
|
buf buf0 (SUM , xor0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, CI );
|
|
and and2 (b_ci , B, CI );
|
|
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
|
|
buf buf1 (COUT , or0_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
|
|
|
|
/**
|
|
* fah: Full adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fah (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM, A, B, CI );
|
|
buf buf0 (SUM , xor0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, CI );
|
|
and and2 (b_ci , B, CI );
|
|
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
|
|
buf buf1 (COUT , or0_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAH_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAH_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAH_1_V
|
|
`define SKY130_FD_SC_HD__FAH_1_V
|
|
|
|
/**
|
|
* fah: Full adder.
|
|
*
|
|
* Verilog wrapper for fah with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fah_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fah base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CI(CI),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fah_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fah base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CI(CI)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAH_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCIN_V
|
|
`define SKY130_FD_SC_HD__FAHCIN_V
|
|
|
|
/**
|
|
* fahcin: Full adder, inverted carry in.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* fahcin: Full adder, inverted carry in.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcin (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire ci ;
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT ;
|
|
wire pwrgood_pp1_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (ci , CIN );
|
|
xor xor0 (xor0_out_SUM , A, B, ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
|
|
buf buf0 (SUM , pwrgood_pp0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, ci );
|
|
and and2 (b_ci , B, ci );
|
|
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
|
|
buf buf1 (COUT , pwrgood_pp1_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* fahcin: Full adder, inverted carry in.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcin (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire ci ;
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT ;
|
|
wire pwrgood_pp1_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (ci , CIN );
|
|
xor xor0 (xor0_out_SUM , A, B, ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
|
|
buf buf0 (SUM , pwrgood_pp0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, ci );
|
|
and and2 (b_ci , B, ci );
|
|
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
|
|
buf buf1 (COUT , pwrgood_pp1_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* fahcin: Full adder, inverted carry in.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcin (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Local signals
|
|
wire ci ;
|
|
wire xor0_out_SUM;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (ci , CIN );
|
|
xor xor0 (xor0_out_SUM, A, B, ci );
|
|
buf buf0 (SUM , xor0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, ci );
|
|
and and2 (b_ci , B, ci );
|
|
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
|
|
buf buf1 (COUT , or0_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* fahcin: Full adder, inverted carry in.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcin (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire ci ;
|
|
wire xor0_out_SUM;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_COUT;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (ci , CIN );
|
|
xor xor0 (xor0_out_SUM, A, B, ci );
|
|
buf buf0 (SUM , xor0_out_SUM );
|
|
and and0 (a_b , A, B );
|
|
and and1 (a_ci , A, ci );
|
|
and and2 (b_ci , B, ci );
|
|
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
|
|
buf buf1 (COUT , or0_out_COUT );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCIN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCIN_1_V
|
|
`define SKY130_FD_SC_HD__FAHCIN_1_V
|
|
|
|
/**
|
|
* fahcin: Full adder, inverted carry in.
|
|
*
|
|
* Verilog wrapper for fahcin with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcin_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fahcin base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcin_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CIN
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CIN ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fahcin base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CIN(CIN)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCIN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCON_V
|
|
`define SKY130_FD_SC_HD__FAHCON_V
|
|
|
|
/**
|
|
* fahcon: Full adder, inverted carry in, inverted carry out.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* fahcon: Full adder, inverted carry in, inverted carry out.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcon (
|
|
COUT_N,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT_N;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_coutn ;
|
|
wire pwrgood_pp1_out_coutn;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM , A, B, CI );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
|
|
buf buf0 (SUM , pwrgood_pp0_out_SUM );
|
|
nor nor0 (a_b , A, B );
|
|
nor nor1 (a_ci , A, CI );
|
|
nor nor2 (b_ci , B, CI );
|
|
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
|
|
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* fahcon: Full adder, inverted carry in, inverted carry out.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcon (
|
|
COUT_N,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT_N;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_coutn ;
|
|
wire pwrgood_pp1_out_coutn;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM , A, B, CI );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
|
|
buf buf0 (SUM , pwrgood_pp0_out_SUM );
|
|
nor nor0 (a_b , A, B );
|
|
nor nor1 (a_ci , A, CI );
|
|
nor nor2 (b_ci , B, CI );
|
|
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
|
|
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
|
|
|
|
/**
|
|
* fahcon: Full adder, inverted carry in, inverted carry out.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcon (
|
|
COUT_N,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI
|
|
);
|
|
|
|
// Module ports
|
|
output COUT_N;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_coutn;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM , A, B, CI );
|
|
buf buf0 (SUM , xor0_out_SUM );
|
|
nor nor0 (a_b , A, B );
|
|
nor nor1 (a_ci , A, CI );
|
|
nor nor2 (b_ci , B, CI );
|
|
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
|
|
buf buf1 (COUT_N , or0_out_coutn );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCON_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
|
|
|
|
/**
|
|
* fahcon: Full adder, inverted carry in, inverted carry out.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcon (
|
|
COUT_N,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI
|
|
);
|
|
|
|
// Module ports
|
|
output COUT_N;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_SUM ;
|
|
wire a_b ;
|
|
wire a_ci ;
|
|
wire b_ci ;
|
|
wire or0_out_coutn;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_SUM , A, B, CI );
|
|
buf buf0 (SUM , xor0_out_SUM );
|
|
nor nor0 (a_b , A, B );
|
|
nor nor1 (a_ci , A, CI );
|
|
nor nor2 (b_ci , B, CI );
|
|
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
|
|
buf buf1 (COUT_N , or0_out_coutn );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCON_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCON_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FAHCON_1_V
|
|
`define SKY130_FD_SC_HD__FAHCON_1_V
|
|
|
|
/**
|
|
* fahcon: Full adder, inverted carry in, inverted carry out.
|
|
*
|
|
* Verilog wrapper for fahcon with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcon_1 (
|
|
COUT_N,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT_N;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fahcon base (
|
|
.COUT_N(COUT_N),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CI(CI),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fahcon_1 (
|
|
COUT_N,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
CI
|
|
);
|
|
|
|
output COUT_N;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input CI ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fahcon base (
|
|
.COUT_N(COUT_N),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.CI(CI)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FAHCON_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_V
|
|
`define SKY130_FD_SC_HD__FILL_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_1_V
|
|
`define SKY130_FD_SC_HD__FILL_1_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog wrapper for fill with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_1 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fill base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_1 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fill base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_2_V
|
|
`define SKY130_FD_SC_HD__FILL_2_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog wrapper for fill with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_2 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fill base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_2 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fill base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_4_V
|
|
`define SKY130_FD_SC_HD__FILL_4_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog wrapper for fill with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_4 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fill base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_4 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fill base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__FILL_8_V
|
|
`define SKY130_FD_SC_HD__FILL_8_V
|
|
|
|
/**
|
|
* fill: Fill cell.
|
|
*
|
|
* Verilog wrapper for fill with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_8 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__fill base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__fill_8 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__fill base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__FILL_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_V
|
|
`define SKY130_FD_SC_HD__HA_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_COUT ;
|
|
wire pwrgood_pp0_out_COUT;
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp1_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_COUT , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
|
|
buf buf0 (COUT , pwrgood_pp0_out_COUT );
|
|
xor xor0 (xor0_out_SUM , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
|
|
buf buf1 (SUM , pwrgood_pp1_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_COUT ;
|
|
wire pwrgood_pp0_out_COUT;
|
|
wire xor0_out_SUM ;
|
|
wire pwrgood_pp1_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_COUT , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
|
|
buf buf0 (COUT , pwrgood_pp0_out_COUT );
|
|
xor xor0 (xor0_out_SUM , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
|
|
buf buf1 (SUM , pwrgood_pp1_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__HA_FUNCTIONAL_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
|
|
// Local signals
|
|
wire and0_out_COUT;
|
|
wire xor0_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_COUT, A, B );
|
|
buf buf0 (COUT , and0_out_COUT );
|
|
xor xor0 (xor0_out_SUM , B, A );
|
|
buf buf1 (SUM , xor0_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__HA_BEHAVIORAL_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_COUT;
|
|
wire xor0_out_SUM ;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_COUT, A, B );
|
|
buf buf0 (COUT , and0_out_COUT );
|
|
xor xor0 (xor0_out_SUM , B, A );
|
|
buf buf1 (SUM , xor0_out_SUM );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_1_V
|
|
`define SKY130_FD_SC_HD__HA_1_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog wrapper for ha with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ha base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha_1 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ha base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_2_V
|
|
`define SKY130_FD_SC_HD__HA_2_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog wrapper for ha with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha_2 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ha base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha_2 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ha base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__HA_4_V
|
|
`define SKY130_FD_SC_HD__HA_4_V
|
|
|
|
/**
|
|
* ha: Half adder.
|
|
*
|
|
* Verilog wrapper for ha with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha_4 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__ha base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__ha_4 (
|
|
COUT,
|
|
SUM ,
|
|
A ,
|
|
B
|
|
);
|
|
|
|
output COUT;
|
|
output SUM ;
|
|
input A ;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__ha base (
|
|
.COUT(COUT),
|
|
.SUM(SUM),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__HA_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_V
|
|
`define SKY130_FD_SC_HD__INV_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__INV_FUNCTIONAL_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__INV_BEHAVIORAL_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_1_V
|
|
`define SKY130_FD_SC_HD__INV_1_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_1 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_1 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_2_V
|
|
`define SKY130_FD_SC_HD__INV_2_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_2 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_2 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_4_V
|
|
`define SKY130_FD_SC_HD__INV_4_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_4 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_4 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_6_V
|
|
`define SKY130_FD_SC_HD__INV_6_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 6 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_6 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_6 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_6_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_8_V
|
|
`define SKY130_FD_SC_HD__INV_8_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_8 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_8 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_12_V
|
|
`define SKY130_FD_SC_HD__INV_12_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 12 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_12 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_12 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_12_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__INV_16_V
|
|
`define SKY130_FD_SC_HD__INV_16_V
|
|
|
|
/**
|
|
* inv: Inverter.
|
|
*
|
|
* Verilog wrapper for inv with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_16 (
|
|
Y ,
|
|
A ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__inv_16 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__inv base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__INV_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
|
|
|
|
/**
|
|
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_bleeder (
|
|
SHORT,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input SHORT;
|
|
inout VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_bleeder (
|
|
SHORT,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input SHORT;
|
|
inout VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
wire gnd;
|
|
|
|
pulldown(gnd);
|
|
bufif1 (VPWR, gnd, SHORT);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_V
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_bleeder (
|
|
SHORT
|
|
);
|
|
|
|
input SHORT;
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_bleeder (
|
|
SHORT
|
|
);
|
|
|
|
input SHORT;
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
|
|
|
|
/**
|
|
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
|
|
*
|
|
* Verilog wrapper for lpflow_bleeder with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_bleeder_1 (
|
|
SHORT,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input SHORT;
|
|
inout VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_bleeder base (
|
|
.SHORT(SHORT),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_bleeder_1 (
|
|
SHORT
|
|
);
|
|
|
|
input SHORT;
|
|
|
|
// Voltage supply signals
|
|
wire VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_bleeder base (
|
|
.SHORT(SHORT)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
|
|
buf buf1 (X , pwrgood0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
|
|
buf buf1 (X , pwrgood0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkbufkapwr with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkbufkapwr with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkbufkapwr with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkbufkapwr with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
|
|
|
|
/**
|
|
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkbufkapwr with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
|
|
X ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
|
|
buf buf0 (Y , pwrgood0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y ;
|
|
wire pwrgood0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y , A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
|
|
buf buf0 (Y , pwrgood0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out_Y, A );
|
|
buf buf0 (Y , not0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkinvkapwr with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkinvkapwr with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkinvkapwr with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkinvkapwr with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
|
|
|
|
/**
|
|
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
|
|
*
|
|
* Verilog wrapper for lpflow_clkinvkapwr with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
|
|
Y ,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
|
|
Y,
|
|
A
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
|
|
.Y(Y),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr ();
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR ;
|
|
supply1 KAPWR;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog wrapper for lpflow_decapkapwr with size of 3 units
|
|
* (invalid?).
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_3 (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base (
|
|
.VPWR(VPWR),
|
|
.KAPWR(KAPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_3 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR ;
|
|
supply1 KAPWR;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog wrapper for lpflow_decapkapwr with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_4 (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base (
|
|
.VPWR(VPWR),
|
|
.KAPWR(KAPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_4 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR ;
|
|
supply1 KAPWR;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog wrapper for lpflow_decapkapwr with size of 6 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_6 (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base (
|
|
.VPWR(VPWR),
|
|
.KAPWR(KAPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_6 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR ;
|
|
supply1 KAPWR;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog wrapper for lpflow_decapkapwr with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_8 (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base (
|
|
.VPWR(VPWR),
|
|
.KAPWR(KAPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_8 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR ;
|
|
supply1 KAPWR;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
|
|
|
|
/**
|
|
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
|
|
* rail.
|
|
*
|
|
* Verilog wrapper for lpflow_decapkapwr with size of 12 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_12 (
|
|
VPWR ,
|
|
KAPWR,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR ;
|
|
input KAPWR;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base (
|
|
.VPWR(VPWR),
|
|
.KAPWR(KAPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_decapkapwr_12 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR ;
|
|
supply1 KAPWR;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_decapkapwr base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
|
|
|
|
/**
|
|
* lpflow_inputiso0n: Input isolator with inverted enable.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso0n: Input isolator with inverted enable.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, A, SLEEP_B );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso0n: Input isolator with inverted enable.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (and0_out_X, A, SLEEP_B );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso0n: Input isolator with inverted enable.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (X , A, SLEEP_B );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso0n: Input isolator with inverted enable.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output Other arguments
|
|
and and0 (X , A, SLEEP_B );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
|
|
|
|
/**
|
|
* lpflow_inputiso0n: Input isolator with inverted enable.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog wrapper for lpflow_inputiso0n with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_inputiso0n base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP_B(SLEEP_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP_B
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_inputiso0n base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP_B(SLEEP_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
|
|
|
|
/**
|
|
* lpflow_inputiso0p: Input isolator with non-inverted enable.
|
|
*
|
|
* X = (A & !SLEEP_B)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso0p: Input isolator with non-inverted enable.
|
|
*
|
|
* X = (A & !SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0p (
|
|
X ,
|
|
A ,
|
|
SLEEP,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire sleepn ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (sleepn , SLEEP );
|
|
and and0 (and0_out_X, A, sleepn );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso0p: Input isolator with non-inverted enable.
|
|
*
|
|
* X = (A & !SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0p (
|
|
X ,
|
|
A ,
|
|
SLEEP,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire sleepn ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (sleepn , SLEEP );
|
|
and and0 (and0_out_X, A, sleepn );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso0p: Input isolator with non-inverted enable.
|
|
*
|
|
* X = (A & !SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0p (
|
|
X ,
|
|
A ,
|
|
SLEEP
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
|
|
// Local signals
|
|
wire sleepn;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (sleepn, SLEEP );
|
|
and and0 (X , A, sleepn );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso0p: Input isolator with non-inverted enable.
|
|
*
|
|
* X = (A & !SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0p (
|
|
X ,
|
|
A ,
|
|
SLEEP
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire sleepn;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (sleepn, SLEEP );
|
|
and and0 (X , A, sleepn );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
|
|
|
|
/**
|
|
* lpflow_inputiso0p: Input isolator with non-inverted enable.
|
|
*
|
|
* X = (A & !SLEEP_B)
|
|
*
|
|
* Verilog wrapper for lpflow_inputiso0p with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0p_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_inputiso0p base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP(SLEEP),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso0p_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_inputiso0p base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP(SLEEP)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
|
|
|
|
/**
|
|
* lpflow_inputiso1n: Input isolation, inverted sleep.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso1n: Input isolation, inverted sleep.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire SLEEP ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SLEEP , SLEEP_B );
|
|
or or0 (or0_out_X, A, SLEEP );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso1n: Input isolation, inverted sleep.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire SLEEP ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SLEEP , SLEEP_B );
|
|
or or0 (or0_out_X, A, SLEEP );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso1n: Input isolation, inverted sleep.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
|
|
// Local signals
|
|
wire SLEEP;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SLEEP , SLEEP_B );
|
|
or or0 (X , A, SLEEP );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso1n: Input isolation, inverted sleep.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1n (
|
|
X ,
|
|
A ,
|
|
SLEEP_B
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire SLEEP;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SLEEP , SLEEP_B );
|
|
or or0 (X , A, SLEEP );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
|
|
|
|
/**
|
|
* lpflow_inputiso1n: Input isolation, inverted sleep.
|
|
*
|
|
* X = (A & SLEEP_B)
|
|
*
|
|
* Verilog wrapper for lpflow_inputiso1n with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1n_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_inputiso1n base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP_B(SLEEP_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1n_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP_B
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_inputiso1n base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP_B(SLEEP_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
|
|
|
|
/**
|
|
* lpflow_inputiso1p: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (A & !SLEEP)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso1p: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (A & !SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1p (
|
|
X ,
|
|
A ,
|
|
SLEEP,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, A, SLEEP );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputiso1p: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (A & !SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1p (
|
|
X ,
|
|
A ,
|
|
SLEEP,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, A, SLEEP );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso1p: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (A & !SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1p (
|
|
X ,
|
|
A ,
|
|
SLEEP
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (X , A, SLEEP );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_inputiso1p: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (A & !SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1p (
|
|
X ,
|
|
A ,
|
|
SLEEP
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (X , A, SLEEP );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
|
|
|
|
/**
|
|
* lpflow_inputiso1p: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (A & !SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_inputiso1p with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1p_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_inputiso1p base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP(SLEEP),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputiso1p_1 (
|
|
X ,
|
|
A ,
|
|
SLEEP
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input SLEEP;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_inputiso1p base (
|
|
.X(X),
|
|
.A(A),
|
|
.SLEEP(SLEEP)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
|
|
|
|
/**
|
|
* lpflow_inputisolatch: Latching input isolator with inverted enable.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputisolatch: Latching input isolator with inverted enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputisolatch (
|
|
Q ,
|
|
D ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D, SLEEP_B, 1'b0, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_inputisolatch: Latching input isolator with inverted enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputisolatch (
|
|
Q ,
|
|
D ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire SLEEP_B_delayed;
|
|
wire D_delayed ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_inputisolatch: Latching input isolator with inverted enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputisolatch (
|
|
Q ,
|
|
D ,
|
|
SLEEP_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input SLEEP_B;
|
|
|
|
// Local signals
|
|
wire buf_Q;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_inputisolatch: Latching input isolator with inverted enable.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputisolatch (
|
|
Q ,
|
|
D ,
|
|
SLEEP_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input D ;
|
|
input SLEEP_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire SLEEP_B_delayed;
|
|
wire D_delayed ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
|
|
|
|
/**
|
|
* lpflow_inputisolatch: Latching input isolator with inverted enable.
|
|
*
|
|
* Verilog wrapper for lpflow_inputisolatch with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
|
|
Q ,
|
|
D ,
|
|
SLEEP_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input SLEEP_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_inputisolatch base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.SLEEP_B(SLEEP_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_inputisolatch_1 (
|
|
Q ,
|
|
D ,
|
|
SLEEP_B
|
|
);
|
|
|
|
output Q ;
|
|
input D ;
|
|
input SLEEP_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_inputisolatch base (
|
|
.Q(Q),
|
|
.D(D),
|
|
.SLEEP_B(SLEEP_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X , not0_out, A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
|
|
buf buf0 (X , pwrgood0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X , not0_out, A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X, and0_out_X, VPWR, VGND, SLEEP);
|
|
buf buf0 (X , pwrgood0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X, not0_out, A );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X, not0_out, A );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_isobufsrc with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_1 (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_isobufsrc with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_isobufsrc with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_4 (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_isobufsrc with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_8 (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_8 (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
|
|
|
|
/**
|
|
* lpflow_isobufsrc: Input isolation, noninverted sleep.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_isobufsrc with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrc_16 (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_isobufsrc base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
|
|
|
|
/**
|
|
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
|
|
* keep-alive power rail.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
|
|
* keep-alive power rail.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood0_out_X ;
|
|
wire pwrgood1_out_x2;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X , not0_out, A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
|
|
buf buf0 (X , pwrgood1_out_x2 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
|
|
* keep-alive power rail.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood0_out_X ;
|
|
wire pwrgood1_out_x2;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X , not0_out, A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
|
|
buf buf0 (X , pwrgood1_out_x2 );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
|
|
* keep-alive power rail.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X, not0_out, A );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
|
|
* keep-alive power rail.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Module supplies
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , SLEEP );
|
|
and and0 (and0_out_X, not0_out, A );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
|
|
|
|
/**
|
|
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
|
|
* keep-alive power rail.
|
|
*
|
|
* X = (!A | SLEEP)
|
|
*
|
|
* Verilog wrapper for lpflow_isobufsrckapwr with size of 16 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
|
|
X ,
|
|
SLEEP,
|
|
A ,
|
|
KAPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
input KAPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A),
|
|
.KAPWR(KAPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
|
|
X ,
|
|
SLEEP,
|
|
A
|
|
);
|
|
|
|
output X ;
|
|
input SLEEP;
|
|
input A ;
|
|
|
|
// Voltage supply signals
|
|
supply1 KAPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
|
|
.X(X),
|
|
.SLEEP(SLEEP),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
|
|
X ,
|
|
A ,
|
|
VPWRIN,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWRIN;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
|
|
// Local signals
|
|
wire pwrgood0_out_A;
|
|
wire buf0_out_X ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
|
|
buf buf0 (buf0_out_X , pwrgood0_out_A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
|
|
X ,
|
|
A ,
|
|
VPWRIN,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VPWRIN;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
|
|
// Local signals
|
|
wire pwrgood0_out_A;
|
|
wire buf0_out_X ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
|
|
buf buf0 (buf0_out_X , pwrgood0_out_A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (X , A );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (X , A );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
|
|
* size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
|
|
X ,
|
|
A ,
|
|
VPWRIN,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWRIN;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWRIN(VPWRIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire VPWRIN;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
|
|
* size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
|
|
X ,
|
|
A ,
|
|
VPWRIN,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWRIN;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWRIN(VPWRIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire VPWRIN;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer,
|
|
* vpb/vnb taps, double-row-height
|
|
* cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
|
|
* size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
|
|
X ,
|
|
A ,
|
|
VPWRIN,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VPWRIN;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
|
|
.X(X),
|
|
.A(A),
|
|
.VPWRIN(VPWRIN),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire VPWRIN;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
|
|
* well on input buffer, no taps,
|
|
* double-row-height cell.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
|
|
* well on input buffer, no taps,
|
|
* double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood0_out_A;
|
|
wire buf0_out_X ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
|
|
buf buf0 (buf0_out_X , pwrgood0_out_A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
|
|
* well on input buffer, no taps,
|
|
* double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire pwrgood0_out_A;
|
|
wire buf0_out_X ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
|
|
buf buf0 (buf0_out_X , pwrgood0_out_A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
|
|
* well on input buffer, no taps,
|
|
* double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (X , A );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
|
|
* well on input buffer, no taps,
|
|
* double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (X , A );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
|
|
* well on input buffer, no taps,
|
|
* double-row-height cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_isowell with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
|
|
.X(X),
|
|
.A(A),
|
|
.LOWLVPWR(LOWLVPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire LOWLVPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
|
|
// Local signals
|
|
wire pwrgood0_out_A;
|
|
wire buf0_out_X ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
|
|
buf buf0 (buf0_out_X , pwrgood0_out_A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
|
|
// Local signals
|
|
wire pwrgood0_out_A;
|
|
wire buf0_out_X ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
|
|
buf buf0 (buf0_out_X , pwrgood0_out_A );
|
|
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (X , A );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (X , A );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
|
|
* size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
|
|
.X(X),
|
|
.A(A),
|
|
.LOWLVPWR(LOWLVPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire LOWLVPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
|
|
* size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
|
|
.X(X),
|
|
.A(A),
|
|
.LOWLVPWR(LOWLVPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire LOWLVPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
|
|
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
|
|
|
|
/**
|
|
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
|
|
* isolated well on input buffer, vpb/vnb
|
|
* taps, double-row-height cell.
|
|
*
|
|
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
|
|
* size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
|
|
X ,
|
|
A ,
|
|
LOWLVPWR,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input LOWLVPWR;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
|
|
.X(X),
|
|
.A(A),
|
|
.LOWLVPWR(LOWLVPWR),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
wire LOWLVPWR;
|
|
supply1 VPWR ;
|
|
supply0 VGND ;
|
|
supply1 VPB ;
|
|
|
|
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_V
|
|
`define SKY130_FD_SC_HD__MACRO_SPARECELL_V
|
|
|
|
/**
|
|
* macro_sparecell: Macro cell for metal-mask-only revisioning,
|
|
* containing inverter, 2-input NOR, 2-input NAND,
|
|
* and constant cell.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* macro_sparecell: Macro cell for metal-mask-only revisioning,
|
|
* containing inverter, 2-input NOR, 2-input NAND,
|
|
* and constant cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import sub cells.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__macro_sparecell (
|
|
LO ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
// Module ports
|
|
output LO ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
|
|
// Local signals
|
|
wire nor2left ;
|
|
wire invleft ;
|
|
wire nor2right;
|
|
wire invright ;
|
|
wire nd2left ;
|
|
wire nd2right ;
|
|
wire tielo ;
|
|
wire net7 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
|
|
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
buf buf0 (LO , tielo );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* macro_sparecell: Macro cell for metal-mask-only revisioning,
|
|
* containing inverter, 2-input NOR, 2-input NAND,
|
|
* and constant cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import sub cells.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__macro_sparecell (
|
|
LO ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
// Module ports
|
|
output LO ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
|
|
// Local signals
|
|
wire nor2left ;
|
|
wire invleft ;
|
|
wire nor2right;
|
|
wire invright ;
|
|
wire nd2left ;
|
|
wire nd2right ;
|
|
wire tielo ;
|
|
wire net7 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
|
|
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
|
|
buf buf0 (LO , tielo );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
|
|
|
|
/**
|
|
* macro_sparecell: Macro cell for metal-mask-only revisioning,
|
|
* containing inverter, 2-input NOR, 2-input NAND,
|
|
* and constant cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import sub cells.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__macro_sparecell (
|
|
LO
|
|
);
|
|
|
|
// Module ports
|
|
output LO;
|
|
|
|
// Local signals
|
|
wire nor2left ;
|
|
wire invleft ;
|
|
wire nor2right;
|
|
wire invright ;
|
|
wire nd2left ;
|
|
wire nd2right ;
|
|
wire tielo ;
|
|
wire net7 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft) );
|
|
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright) );
|
|
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) );
|
|
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right));
|
|
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) );
|
|
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) );
|
|
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7) );
|
|
buf buf0 (LO , tielo );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
|
|
|
|
/**
|
|
* macro_sparecell: Macro cell for metal-mask-only revisioning,
|
|
* containing inverter, 2-input NOR, 2-input NAND,
|
|
* and constant cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import sub cells.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__macro_sparecell (
|
|
LO
|
|
);
|
|
|
|
// Module ports
|
|
output LO;
|
|
|
|
// Local signals
|
|
wire nor2left ;
|
|
wire invleft ;
|
|
wire nor2right;
|
|
wire invright ;
|
|
wire nd2left ;
|
|
wire nd2right ;
|
|
wire tielo ;
|
|
wire net7 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft) );
|
|
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright) );
|
|
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) );
|
|
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right));
|
|
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) );
|
|
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) );
|
|
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7) );
|
|
buf buf0 (LO , tielo );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_V
|
|
`define SKY130_FD_SC_HD__MAJ3_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or1_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B, A );
|
|
and and0 (and0_out , or0_out, C );
|
|
and and1 (and1_out , A, B );
|
|
or or1 (or1_out_X , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or1_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B, A );
|
|
and and0 (and0_out , or0_out, C );
|
|
and and1 (and1_out , A, B );
|
|
or or1 (or1_out_X , and1_out, and0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or1_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B, A );
|
|
and and0 (and0_out , or0_out, C );
|
|
and and1 (and1_out , A, B );
|
|
or or1 (or1_out_X, and1_out, and0_out);
|
|
buf buf0 (X , or1_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out ;
|
|
wire and1_out ;
|
|
wire or1_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B, A );
|
|
and and0 (and0_out , or0_out, C );
|
|
and and1 (and1_out , A, B );
|
|
or or1 (or1_out_X, and1_out, and0_out);
|
|
buf buf0 (X , or1_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_1_V
|
|
`define SKY130_FD_SC_HD__MAJ3_1_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog wrapper for maj3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__maj3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__maj3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_2_V
|
|
`define SKY130_FD_SC_HD__MAJ3_2_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog wrapper for maj3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__maj3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__maj3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MAJ3_4_V
|
|
`define SKY130_FD_SC_HD__MAJ3_4_V
|
|
|
|
/**
|
|
* maj3: 3-input majority vote.
|
|
*
|
|
* Verilog wrapper for maj3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__maj3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__maj3_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__maj3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MAJ3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_V
|
|
`define SKY130_FD_SC_HD__MUX2_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire mux_2to10_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire mux_2to10_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Local signals
|
|
wire mux_2to10_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
|
|
buf buf0 (X , mux_2to10_out_X);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire mux_2to10_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
|
|
buf buf0 (X , mux_2to10_out_X);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_1_V
|
|
`define SKY130_FD_SC_HD__MUX2_1_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_1 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_1 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_2_V
|
|
`define SKY130_FD_SC_HD__MUX2_2_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_2 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_2 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_4_V
|
|
`define SKY130_FD_SC_HD__MUX2_4_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_4 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_4 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2_8_V
|
|
`define SKY130_FD_SC_HD__MUX2_8_V
|
|
|
|
/**
|
|
* mux2: 2-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux2 with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_8 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2_8 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_V
|
|
`define SKY130_FD_SC_HD__MUX2I_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i (
|
|
Y ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire mux_2to1_n0_out_Y;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i (
|
|
Y ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire mux_2to1_n0_out_Y;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i (
|
|
Y ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Local signals
|
|
wire mux_2to1_n0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
|
|
buf buf0 (Y , mux_2to1_n0_out_Y);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i (
|
|
Y ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire mux_2to1_n0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
|
|
buf buf0 (Y , mux_2to1_n0_out_Y);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_1_V
|
|
`define SKY130_FD_SC_HD__MUX2I_1_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog wrapper for mux2i with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i_1 (
|
|
Y ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2i base (
|
|
.Y(Y),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i_1 (
|
|
Y ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output Y ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2i base (
|
|
.Y(Y),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_2_V
|
|
`define SKY130_FD_SC_HD__MUX2I_2_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog wrapper for mux2i with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i_2 (
|
|
Y ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2i base (
|
|
.Y(Y),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i_2 (
|
|
Y ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output Y ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2i base (
|
|
.Y(Y),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX2I_4_V
|
|
`define SKY130_FD_SC_HD__MUX2I_4_V
|
|
|
|
/**
|
|
* mux2i: 2-input multiplexer, output inverted.
|
|
*
|
|
* Verilog wrapper for mux2i with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i_4 (
|
|
Y ,
|
|
A0 ,
|
|
A1 ,
|
|
S ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input S ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux2i base (
|
|
.Y(Y),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux2i_4 (
|
|
Y ,
|
|
A0,
|
|
A1,
|
|
S
|
|
);
|
|
|
|
output Y ;
|
|
input A0;
|
|
input A1;
|
|
input S ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux2i base (
|
|
.Y(Y),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.S(S)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX2I_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_V
|
|
`define SKY130_FD_SC_HD__MUX4_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
S0 ,
|
|
S1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input S0 ;
|
|
input S1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire mux_4to20_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
S0 ,
|
|
S1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input S0 ;
|
|
input S1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire mux_4to20_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
S0,
|
|
S1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input S0;
|
|
input S1;
|
|
|
|
// Local signals
|
|
wire mux_4to20_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
|
|
buf buf0 (X , mux_4to20_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
S0,
|
|
S1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input S0;
|
|
input S1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire mux_4to20_out_X;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
|
|
buf buf0 (X , mux_4to20_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_1_V
|
|
`define SKY130_FD_SC_HD__MUX4_1_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux4 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4_1 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
S0 ,
|
|
S1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input S0 ;
|
|
input S1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux4 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.S0(S0),
|
|
.S1(S1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4_1 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
S0,
|
|
S1
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input S0;
|
|
input S1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux4 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.S0(S0),
|
|
.S1(S1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_2_V
|
|
`define SKY130_FD_SC_HD__MUX4_2_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux4 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4_2 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
S0 ,
|
|
S1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input S0 ;
|
|
input S1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux4 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.S0(S0),
|
|
.S1(S1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4_2 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
S0,
|
|
S1
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input S0;
|
|
input S1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux4 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.S0(S0),
|
|
.S1(S1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__MUX4_4_V
|
|
`define SKY130_FD_SC_HD__MUX4_4_V
|
|
|
|
/**
|
|
* mux4: 4-input multiplexer.
|
|
*
|
|
* Verilog wrapper for mux4 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4_4 (
|
|
X ,
|
|
A0 ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
S0 ,
|
|
S1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A0 ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input S0 ;
|
|
input S1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__mux4 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.S0(S0),
|
|
.S1(S1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__mux4_4 (
|
|
X ,
|
|
A0,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
S0,
|
|
S1
|
|
);
|
|
|
|
output X ;
|
|
input A0;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input S0;
|
|
input S1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__mux4 base (
|
|
.X(X),
|
|
.A0(A0),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.S0(S0),
|
|
.S1(S1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__MUX4_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_V
|
|
`define SKY130_FD_SC_HD__NAND2_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y, B, A );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y, B, A );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_1_V
|
|
`define SKY130_FD_SC_HD__NAND2_1_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog wrapper for nand2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_1 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_2_V
|
|
`define SKY130_FD_SC_HD__NAND2_2_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog wrapper for nand2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_4_V
|
|
`define SKY130_FD_SC_HD__NAND2_4_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog wrapper for nand2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_4 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2_8_V
|
|
`define SKY130_FD_SC_HD__NAND2_8_V
|
|
|
|
/**
|
|
* nand2: 2-input NAND.
|
|
*
|
|
* Verilog wrapper for nand2 with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_8 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2_8 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_V
|
|
`define SKY130_FD_SC_HD__NAND2B_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B );
|
|
or or0 (or0_out_Y , not0_out, A_N );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B );
|
|
or or0 (or0_out_Y , not0_out, A_N );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b (
|
|
Y ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B );
|
|
or or0 (or0_out_Y, not0_out, A_N );
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b (
|
|
Y ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B );
|
|
or or0 (or0_out_Y, not0_out, A_N );
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_1_V
|
|
`define SKY130_FD_SC_HD__NAND2B_1_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand2b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b_1 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b_1 (
|
|
Y ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_2_V
|
|
`define SKY130_FD_SC_HD__NAND2B_2_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand2b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b_2 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b_2 (
|
|
Y ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND2B_4_V
|
|
`define SKY130_FD_SC_HD__NAND2B_4_V
|
|
|
|
/**
|
|
* nand2b: 2-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand2b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b_4 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand2b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand2b_4 (
|
|
Y ,
|
|
A_N,
|
|
B
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand2b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND2B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_V
|
|
`define SKY130_FD_SC_HD__NAND3_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y , B, A, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y , B, A, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y, B, A, C );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y, B, A, C );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_1_V
|
|
`define SKY130_FD_SC_HD__NAND3_1_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog wrapper for nand3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3_1 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_2_V
|
|
`define SKY130_FD_SC_HD__NAND3_2_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog wrapper for nand3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3_2 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3_4_V
|
|
`define SKY130_FD_SC_HD__NAND3_4_V
|
|
|
|
/**
|
|
* nand3: 3-input NAND.
|
|
*
|
|
* Verilog wrapper for nand3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3_4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_V
|
|
`define SKY130_FD_SC_HD__NAND3B_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y , B, not0_out, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y , B, not0_out, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y, B, not0_out, C );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y, B, not0_out, C );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_1_V
|
|
`define SKY130_FD_SC_HD__NAND3B_1_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand3b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b_1 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand3b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b_1 (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand3b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_2_V
|
|
`define SKY130_FD_SC_HD__NAND3B_2_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand3b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b_2 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand3b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b_2 (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand3b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND3B_4_V
|
|
`define SKY130_FD_SC_HD__NAND3B_4_V
|
|
|
|
/**
|
|
* nand3b: 3-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand3b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b_4 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand3b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand3b_4 (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand3b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND3B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_V
|
|
`define SKY130_FD_SC_HD__NAND4_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y , D, C, B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y , D, C, B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y, D, C, B, A );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out_Y, D, C, B, A );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_1_V
|
|
`define SKY130_FD_SC_HD__NAND4_1_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog wrapper for nand4 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4_1 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_2_V
|
|
`define SKY130_FD_SC_HD__NAND4_2_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog wrapper for nand4 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4_2 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4_4_V
|
|
`define SKY130_FD_SC_HD__NAND4_4_V
|
|
|
|
/**
|
|
* nand4: 4-input NAND.
|
|
*
|
|
* Verilog wrapper for nand4 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4_4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_V
|
|
`define SKY130_FD_SC_HD__NAND4B_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y , D, C, B, not0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y , D, C, B, not0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y, D, C, B, not0_out);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A_N );
|
|
nand nand0 (nand0_out_Y, D, C, B, not0_out);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_1_V
|
|
`define SKY130_FD_SC_HD__NAND4B_1_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand4b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b_1 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b_1 (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_2_V
|
|
`define SKY130_FD_SC_HD__NAND4B_2_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand4b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b_2 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b_2 (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4B_4_V
|
|
`define SKY130_FD_SC_HD__NAND4B_4_V
|
|
|
|
/**
|
|
* nand4b: 4-input NAND, first input inverted.
|
|
*
|
|
* Verilog wrapper for nand4b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b_4 (
|
|
Y ,
|
|
A_N ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4b_4 (
|
|
Y ,
|
|
A_N,
|
|
B ,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4b base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb (
|
|
Y ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , D, C );
|
|
or or0 (or0_out_Y , B_N, A_N, nand0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb (
|
|
Y ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , D, C );
|
|
or or0 (or0_out_Y , B_N, A_N, nand0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb (
|
|
Y ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Local signals
|
|
wire nand0_out;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out, D, C );
|
|
or or0 (or0_out_Y, B_N, A_N, nand0_out);
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb (
|
|
Y ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out, D, C );
|
|
or or0 (or0_out_Y, B_N, A_N, nand0_out);
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_1_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_1_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for nand4bb with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb_1 (
|
|
Y ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4bb base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb_1 (
|
|
Y ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4bb base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_2_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_2_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for nand4bb with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb_2 (
|
|
Y ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4bb base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb_2 (
|
|
Y ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4bb base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NAND4BB_4_V
|
|
`define SKY130_FD_SC_HD__NAND4BB_4_V
|
|
|
|
/**
|
|
* nand4bb: 4-input NAND, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for nand4bb with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb_4 (
|
|
Y ,
|
|
A_N ,
|
|
B_N ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A_N ;
|
|
input B_N ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nand4bb base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nand4bb_4 (
|
|
Y ,
|
|
A_N,
|
|
B_N,
|
|
C ,
|
|
D
|
|
);
|
|
|
|
output Y ;
|
|
input A_N;
|
|
input B_N;
|
|
input C ;
|
|
input D ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nand4bb base (
|
|
.Y(Y),
|
|
.A_N(A_N),
|
|
.B_N(B_N),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NAND4BB_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_V
|
|
`define SKY130_FD_SC_HD__NOR2_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y, A, B );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y, A, B );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_1_V
|
|
`define SKY130_FD_SC_HD__NOR2_1_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog wrapper for nor2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_1 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_2_V
|
|
`define SKY130_FD_SC_HD__NOR2_2_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog wrapper for nor2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_4_V
|
|
`define SKY130_FD_SC_HD__NOR2_4_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog wrapper for nor2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_4 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2_8_V
|
|
`define SKY130_FD_SC_HD__NOR2_8_V
|
|
|
|
/**
|
|
* nor2: 2-input NOR.
|
|
*
|
|
* Verilog wrapper for nor2 with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_8 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2_8 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_V
|
|
`define SKY130_FD_SC_HD__NOR2B_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b (
|
|
Y ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A );
|
|
and and0 (and0_out_Y , not0_out, B_N );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b (
|
|
Y ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A );
|
|
and and0 (and0_out_Y , not0_out, B_N );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b (
|
|
Y ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A );
|
|
and and0 (and0_out_Y, not0_out, B_N );
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b (
|
|
Y ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , A );
|
|
and and0 (and0_out_Y, not0_out, B_N );
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_1_V
|
|
`define SKY130_FD_SC_HD__NOR2B_1_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog wrapper for nor2b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b_1 (
|
|
Y ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B_N(B_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b_1 (
|
|
Y ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B_N(B_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_2_V
|
|
`define SKY130_FD_SC_HD__NOR2B_2_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog wrapper for nor2b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b_2 (
|
|
Y ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B_N(B_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b_2 (
|
|
Y ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B_N(B_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR2B_4_V
|
|
`define SKY130_FD_SC_HD__NOR2B_4_V
|
|
|
|
/**
|
|
* nor2b: 2-input NOR, first input inverted.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog wrapper for nor2b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b_4 (
|
|
Y ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor2b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B_N(B_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor2b_4 (
|
|
Y ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor2b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B_N(B_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR2B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_V
|
|
`define SKY130_FD_SC_HD__NOR3_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y , C, A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y , C, A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y, C, A, B );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y, C, A, B );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_1_V
|
|
`define SKY130_FD_SC_HD__NOR3_1_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog wrapper for nor3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3_1 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_2_V
|
|
`define SKY130_FD_SC_HD__NOR3_2_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog wrapper for nor3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3_2 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3_4_V
|
|
`define SKY130_FD_SC_HD__NOR3_4_V
|
|
|
|
/**
|
|
* nor3: 3-input NOR.
|
|
*
|
|
* Y = !(A | B | C | !D)
|
|
*
|
|
* Verilog wrapper for nor3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3_4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor3 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_V
|
|
`define SKY130_FD_SC_HD__NOR3B_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y , C_N, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y , C_N, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y, C_N, nor0_out );
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y, C_N, nor0_out );
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_1_V
|
|
`define SKY130_FD_SC_HD__NOR3B_1_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog wrapper for nor3b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor3b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor3b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_2_V
|
|
`define SKY130_FD_SC_HD__NOR3B_2_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog wrapper for nor3b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor3b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor3b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR3B_4_V
|
|
`define SKY130_FD_SC_HD__NOR3B_4_V
|
|
|
|
/**
|
|
* nor3b: 3-input NOR, first input inverted.
|
|
*
|
|
* Y = (!(A | B)) & !C)
|
|
*
|
|
* Verilog wrapper for nor3b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor3b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor3b_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor3b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR3B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_V
|
|
`define SKY130_FD_SC_HD__NOR4_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y , A, B, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y , A, B, C, D );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y, A, B, C, D );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out_Y, A, B, C, D );
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_1_V
|
|
`define SKY130_FD_SC_HD__NOR4_1_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog wrapper for nor4 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4_1 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_2_V
|
|
`define SKY130_FD_SC_HD__NOR4_2_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog wrapper for nor4 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4_2 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4_4_V
|
|
`define SKY130_FD_SC_HD__NOR4_4_V
|
|
|
|
/**
|
|
* nor4: 4-input NOR.
|
|
*
|
|
* Y = !(A | B | C | D)
|
|
*
|
|
* Verilog wrapper for nor4 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4_4 (
|
|
Y,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_V
|
|
`define SKY130_FD_SC_HD__NOR4B_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
nor nor0 (nor0_out_Y , A, B, C, not0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
nor nor0 (nor0_out_Y , A, B, C, not0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
nor nor0 (nor0_out_Y, A, B, C, not0_out);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire nor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
nor nor0 (nor0_out_Y, A, B, C, not0_out);
|
|
buf buf0 (Y , nor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_1_V
|
|
`define SKY130_FD_SC_HD__NOR4B_1_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog wrapper for nor4b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_2_V
|
|
`define SKY130_FD_SC_HD__NOR4B_2_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog wrapper for nor4b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4B_4_V
|
|
`define SKY130_FD_SC_HD__NOR4B_4_V
|
|
|
|
/**
|
|
* nor4b: 4-input NOR, first input inverted.
|
|
*
|
|
* Verilog wrapper for nor4b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4b_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4b base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y , nor0_out, C_N, D_N );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y , nor0_out, C_N, D_N );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y, nor0_out, C_N, D_N);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire and0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A, B );
|
|
and and0 (and0_out_Y, nor0_out, C_N, D_N);
|
|
buf buf0 (Y , and0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_1_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_1_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for nor4bb with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4bb base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4bb base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_2_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_2_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for nor4bb with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4bb base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4bb base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__NOR4BB_4_V
|
|
`define SKY130_FD_SC_HD__NOR4BB_4_V
|
|
|
|
/**
|
|
* nor4bb: 4-input NOR, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for nor4bb with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__nor4bb base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__nor4bb_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__nor4bb base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__NOR4BB_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
and and0 (and0_out_X , nand0_out, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
and and0 (and0_out_X , nand0_out, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
and and0 (and0_out_X, nand0_out, or0_out);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
and and0 (and0_out_X, nand0_out, or0_out);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_1_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_1_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o2bb2a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a_1 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2bb2a base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a_1 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2bb2a base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_2_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_2_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o2bb2a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a_2 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2bb2a base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a_2 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2bb2a base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2A_4_V
|
|
`define SKY130_FD_SC_HD__O2BB2A_4_V
|
|
|
|
/**
|
|
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
|
|
*
|
|
* X = (!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o2bb2a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a_4 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2bb2a base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2a_4 (
|
|
X ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2bb2a base (
|
|
.X(X),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire nand1_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
nand nand1 (nand1_out_Y , nand0_out, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire nand1_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
nand nand1 (nand1_out_Y , nand0_out, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire nand1_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
nand nand1 (nand1_out_Y, nand0_out, or0_out);
|
|
buf buf0 (Y , nand1_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out ;
|
|
wire nand1_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , A2_N, A1_N );
|
|
or or0 (or0_out , B2, B1 );
|
|
nand nand1 (nand1_out_Y, nand0_out, or0_out);
|
|
buf buf0 (Y , nand1_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_1_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_1_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o2bb2ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai_1 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2bb2ai base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai_1 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2bb2ai base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_2_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_2_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o2bb2ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai_2 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2bb2ai base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai_2 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2bb2ai base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2BB2AI_4_V
|
|
`define SKY130_FD_SC_HD__O2BB2AI_4_V
|
|
|
|
/**
|
|
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !(!(A1 & A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o2bb2ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai_4 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2bb2ai base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2bb2ai_4 (
|
|
Y ,
|
|
A1_N,
|
|
A2_N,
|
|
B1 ,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1_N;
|
|
input A2_N;
|
|
input B1 ;
|
|
input B2 ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2bb2ai base (
|
|
.Y(Y),
|
|
.A1_N(A1_N),
|
|
.A2_N(A2_N),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2BB2AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_V
|
|
`define SKY130_FD_SC_HD__O21A_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X , or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X , or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X, or0_out, B1 );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X, or0_out, B1 );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_1_V
|
|
`define SKY130_FD_SC_HD__O21A_1_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_2_V
|
|
`define SKY130_FD_SC_HD__O21A_2_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21A_4_V
|
|
`define SKY130_FD_SC_HD__O21A_4_V
|
|
|
|
/**
|
|
* o21a: 2-input OR into first input of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_V
|
|
`define SKY130_FD_SC_HD__O21AI_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , B1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , B1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, B1, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, B1, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_0_V
|
|
`define SKY130_FD_SC_HD__O21AI_0_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21ai with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_0 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_0 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_1_V
|
|
`define SKY130_FD_SC_HD__O21AI_1_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_2_V
|
|
`define SKY130_FD_SC_HD__O21AI_2_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21AI_4_V
|
|
`define SKY130_FD_SC_HD__O21AI_4_V
|
|
|
|
/**
|
|
* o21ai: 2-input OR into first input of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1)
|
|
*
|
|
* Verilog wrapper for o21ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_V
|
|
`define SKY130_FD_SC_HD__O21BA_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A1, A2 );
|
|
nor nor1 (nor1_out_X , B1_N, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A1, A2 );
|
|
nor nor1 (nor1_out_X , B1_N, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A1, A2 );
|
|
nor nor1 (nor1_out_X, B1_N, nor0_out );
|
|
buf buf0 (X , nor1_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A1, A2 );
|
|
nor nor1 (nor1_out_X, B1_N, nor0_out );
|
|
buf buf0 (X , nor1_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_1_V
|
|
`define SKY130_FD_SC_HD__O21BA_1_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog wrapper for o21ba with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ba base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ba base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_2_V
|
|
`define SKY130_FD_SC_HD__O21BA_2_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog wrapper for o21ba with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ba base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ba base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BA_4_V
|
|
`define SKY130_FD_SC_HD__O21BA_4_V
|
|
|
|
/**
|
|
* o21ba: 2-input OR into first input of 2-input AND,
|
|
* 2nd input inverted.
|
|
*
|
|
* X = ((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog wrapper for o21ba with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21ba base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21ba_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21ba base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BA_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_V
|
|
`define SKY130_FD_SC_HD__O21BAI_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , b, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , b, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, b, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire b ;
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (b , B1_N );
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, b, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_1_V
|
|
`define SKY130_FD_SC_HD__O21BAI_1_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog wrapper for o21bai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21bai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21bai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_2_V
|
|
`define SKY130_FD_SC_HD__O21BAI_2_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog wrapper for o21bai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21bai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21bai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O21BAI_4_V
|
|
`define SKY130_FD_SC_HD__O21BAI_4_V
|
|
|
|
/**
|
|
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
|
|
* inverted.
|
|
*
|
|
* Y = !((A1 | A2) & !B1_N)
|
|
*
|
|
* Verilog wrapper for o21bai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o21bai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o21bai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1_N
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o21bai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1_N(B1_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O21BAI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_V
|
|
`define SKY130_FD_SC_HD__O22A_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X , or0_out, or1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X , or0_out, or1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X, or0_out, or1_out);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X, or0_out, or1_out);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_1_V
|
|
`define SKY130_FD_SC_HD__O22A_1_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o22a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o22a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o22a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_2_V
|
|
`define SKY130_FD_SC_HD__O22A_2_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o22a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o22a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o22a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22A_4_V
|
|
`define SKY130_FD_SC_HD__O22A_4_V
|
|
|
|
/**
|
|
* o22a: 2-input OR into both inputs of 2-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o22a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o22a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o22a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_V
|
|
`define SKY130_FD_SC_HD__O22AI_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , B1, B2 );
|
|
nor nor1 (nor1_out , A1, A2 );
|
|
or or0 (or0_out_Y , nor1_out, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , B1, B2 );
|
|
nor nor1 (nor1_out , A1, A2 );
|
|
or or0 (or0_out_Y , nor1_out, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , B1, B2 );
|
|
nor nor1 (nor1_out , A1, A2 );
|
|
or or0 (or0_out_Y, nor1_out, nor0_out);
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , B1, B2 );
|
|
nor nor1 (nor1_out , A1, A2 );
|
|
or or0 (or0_out_Y, nor1_out, nor0_out);
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_1_V
|
|
`define SKY130_FD_SC_HD__O22AI_1_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o22ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o22ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o22ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_2_V
|
|
`define SKY130_FD_SC_HD__O22AI_2_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o22ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o22ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o22ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O22AI_4_V
|
|
`define SKY130_FD_SC_HD__O22AI_4_V
|
|
|
|
/**
|
|
* o22ai: 2-input OR into both inputs of 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o22ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o22ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o22ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o22ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O22AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_V
|
|
`define SKY130_FD_SC_HD__O31A_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X , or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X , or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X, or0_out, B1 );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X, or0_out, B1 );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_1_V
|
|
`define SKY130_FD_SC_HD__O31A_1_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog wrapper for o31a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o31a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o31a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_2_V
|
|
`define SKY130_FD_SC_HD__O31A_2_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog wrapper for o31a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o31a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o31a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31A_4_V
|
|
`define SKY130_FD_SC_HD__O31A_4_V
|
|
|
|
/**
|
|
* o31a: 3-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog wrapper for o31a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o31a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o31a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_V
|
|
`define SKY130_FD_SC_HD__O31AI_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y , B1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y , B1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y, B1, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y, B1, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_1_V
|
|
`define SKY130_FD_SC_HD__O31AI_1_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog wrapper for o31ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o31ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o31ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_2_V
|
|
`define SKY130_FD_SC_HD__O31AI_2_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog wrapper for o31ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o31ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o31ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O31AI_4_V
|
|
`define SKY130_FD_SC_HD__O31AI_4_V
|
|
|
|
/**
|
|
* o31ai: 3-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1)
|
|
*
|
|
* Verilog wrapper for o31ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o31ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o31ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o31ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O31AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_V
|
|
`define SKY130_FD_SC_HD__O32A_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X , or0_out, or1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X , or0_out, or1_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X, or0_out, or1_out);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
or or1 (or1_out , B2, B1 );
|
|
and and0 (and0_out_X, or0_out, or1_out);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_1_V
|
|
`define SKY130_FD_SC_HD__O32A_1_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o32a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o32a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o32a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_2_V
|
|
`define SKY130_FD_SC_HD__O32A_2_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o32a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o32a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o32a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32A_4_V
|
|
`define SKY130_FD_SC_HD__O32A_4_V
|
|
|
|
/**
|
|
* o32a: 3-input OR and 2-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o32a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o32a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o32a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_V
|
|
`define SKY130_FD_SC_HD__O32AI_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A3, A1, A2 );
|
|
nor nor1 (nor1_out , B1, B2 );
|
|
or or0 (or0_out_Y , nor1_out, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A3, A1, A2 );
|
|
nor nor1 (nor1_out , B1, B2 );
|
|
or or0 (or0_out_Y , nor1_out, nor0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A3, A1, A2 );
|
|
nor nor1 (nor1_out , B1, B2 );
|
|
or or0 (or0_out_Y, nor1_out, nor0_out);
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nor0_out ;
|
|
wire nor1_out ;
|
|
wire or0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
nor nor0 (nor0_out , A3, A1, A2 );
|
|
nor nor1 (nor1_out , B1, B2 );
|
|
or or0 (or0_out_Y, nor1_out, nor0_out);
|
|
buf buf0 (Y , or0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_1_V
|
|
`define SKY130_FD_SC_HD__O32AI_1_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o32ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o32ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o32ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_2_V
|
|
`define SKY130_FD_SC_HD__O32AI_2_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o32ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o32ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o32ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O32AI_4_V
|
|
`define SKY130_FD_SC_HD__O32AI_4_V
|
|
|
|
/**
|
|
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & (B1 | B2))
|
|
*
|
|
* Verilog wrapper for o32ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
B2 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o32ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o32ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
B2
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input B2;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o32ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.B2(B2)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O32AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_V
|
|
`define SKY130_FD_SC_HD__O41A_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
and and0 (and0_out_X , or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
and and0 (and0_out_X , or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
and and0 (and0_out_X, or0_out, B1 );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
and and0 (and0_out_X, or0_out, B1 );
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_1_V
|
|
`define SKY130_FD_SC_HD__O41A_1_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog wrapper for o41a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o41a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o41a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_2_V
|
|
`define SKY130_FD_SC_HD__O41A_2_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog wrapper for o41a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o41a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o41a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41A_4_V
|
|
`define SKY130_FD_SC_HD__O41A_4_V
|
|
|
|
/**
|
|
* o41a: 4-input OR into 2-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog wrapper for o41a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o41a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o41a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_V
|
|
`define SKY130_FD_SC_HD__O41AI_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
nand nand0 (nand0_out_Y , B1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
nand nand0 (nand0_out_Y , B1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
nand nand0 (nand0_out_Y, B1, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A4, A3, A2, A1 );
|
|
nand nand0 (nand0_out_Y, B1, or0_out );
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_1_V
|
|
`define SKY130_FD_SC_HD__O41AI_1_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog wrapper for o41ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o41ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o41ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_2_V
|
|
`define SKY130_FD_SC_HD__O41AI_2_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog wrapper for o41ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o41ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o41ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O41AI_4_V
|
|
`define SKY130_FD_SC_HD__O41AI_4_V
|
|
|
|
/**
|
|
* o41ai: 4-input OR into 2-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3 | A4) & B1)
|
|
*
|
|
* Verilog wrapper for o41ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
A4 ,
|
|
B1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input A4 ;
|
|
input B1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o41ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o41ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
A4,
|
|
B1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input A4;
|
|
input B1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o41ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.A4(A4),
|
|
.B1(B1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O41AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_V
|
|
`define SKY130_FD_SC_HD__O211A_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X , or0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X , or0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X, or0_out, B1, C1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X, or0_out, B1, C1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_1_V
|
|
`define SKY130_FD_SC_HD__O211A_1_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o211a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o211a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o211a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_2_V
|
|
`define SKY130_FD_SC_HD__O211A_2_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o211a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o211a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o211a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211A_4_V
|
|
`define SKY130_FD_SC_HD__O211A_4_V
|
|
|
|
/**
|
|
* o211a: 2-input OR into first input of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o211a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o211a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o211a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_V
|
|
`define SKY130_FD_SC_HD__O211AI_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, C1, or0_out, B1);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, C1, or0_out, B1);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_1_V
|
|
`define SKY130_FD_SC_HD__O211AI_1_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o211ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o211ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o211ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_2_V
|
|
`define SKY130_FD_SC_HD__O211AI_2_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o211ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o211ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o211ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O211AI_4_V
|
|
`define SKY130_FD_SC_HD__O211AI_4_V
|
|
|
|
/**
|
|
* o211ai: 2-input OR into first input of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o211ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o211ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o211ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o211ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O211AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_V
|
|
`define SKY130_FD_SC_HD__O221A_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
and and0 (and0_out_X , or0_out, or1_out, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
and and0 (and0_out_X , or0_out, or1_out, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
and and0 (and0_out_X, or0_out, or1_out, C1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
and and0 (and0_out_X, or0_out, or1_out, C1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_1_V
|
|
`define SKY130_FD_SC_HD__O221A_1_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog wrapper for o221a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o221a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o221a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_2_V
|
|
`define SKY130_FD_SC_HD__O221A_2_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog wrapper for o221a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o221a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o221a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221A_4_V
|
|
`define SKY130_FD_SC_HD__O221A_4_V
|
|
|
|
/**
|
|
* o221a: 2-input OR into first two inputs of 3-input AND.
|
|
*
|
|
* X = ((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog wrapper for o221a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o221a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o221a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_V
|
|
`define SKY130_FD_SC_HD__O221AI_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire or1_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , B2, B1 );
|
|
or or1 (or1_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_1_V
|
|
`define SKY130_FD_SC_HD__O221AI_1_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog wrapper for o221ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o221ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o221ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_2_V
|
|
`define SKY130_FD_SC_HD__O221AI_2_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog wrapper for o221ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o221ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o221ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O221AI_4_V
|
|
`define SKY130_FD_SC_HD__O221AI_4_V
|
|
|
|
/**
|
|
* o221ai: 2-input OR into first two inputs of 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & (B1 | B2) & C1)
|
|
*
|
|
* Verilog wrapper for o221ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
B2 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input B2 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o221ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o221ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
B2,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input B2;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o221ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.B2(B2),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O221AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_V
|
|
`define SKY130_FD_SC_HD__O311A_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X , or0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X , or0_out, B1, C1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X, or0_out, B1, C1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
and and0 (and0_out_X, or0_out, B1, C1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_1_V
|
|
`define SKY130_FD_SC_HD__O311A_1_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_2_V
|
|
`define SKY130_FD_SC_HD__O311A_2_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311A_4_V
|
|
`define SKY130_FD_SC_HD__O311A_4_V
|
|
|
|
/**
|
|
* o311a: 3-input OR into 3-input AND.
|
|
*
|
|
* X = ((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_V
|
|
`define SKY130_FD_SC_HD__O311AI_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y, C1, or0_out, B1);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1, A3 );
|
|
nand nand0 (nand0_out_Y, C1, or0_out, B1);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_0_V
|
|
`define SKY130_FD_SC_HD__O311AI_0_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311ai with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_0 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_0 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_1_V
|
|
`define SKY130_FD_SC_HD__O311AI_1_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_2_V
|
|
`define SKY130_FD_SC_HD__O311AI_2_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O311AI_4_V
|
|
`define SKY130_FD_SC_HD__O311AI_4_V
|
|
|
|
/**
|
|
* o311ai: 3-input OR into 3-input NAND.
|
|
*
|
|
* Y = !((A1 | A2 | A3) & B1 & C1)
|
|
*
|
|
* Verilog wrapper for o311ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
A3 ,
|
|
B1 ,
|
|
C1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input A3 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o311ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
A3,
|
|
B1,
|
|
C1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input A3;
|
|
input B1;
|
|
input C1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o311ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.A3(A3),
|
|
.B1(B1),
|
|
.C1(C1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O311AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_V
|
|
`define SKY130_FD_SC_HD__O2111A_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X , B1, C1, or0_out, D1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X , B1, C1, or0_out, D1 );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X, B1, C1, or0_out, D1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire and0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
and and0 (and0_out_X, B1, C1, or0_out, D1);
|
|
buf buf0 (X , and0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_1_V
|
|
`define SKY130_FD_SC_HD__O2111A_1_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog wrapper for o2111a with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a_1 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2111a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a_1 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2111a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_2_V
|
|
`define SKY130_FD_SC_HD__O2111A_2_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog wrapper for o2111a with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a_2 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2111a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a_2 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2111a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111A_4_V
|
|
`define SKY130_FD_SC_HD__O2111A_4_V
|
|
|
|
/**
|
|
* o2111a: 2-input OR into first input of 4-input AND.
|
|
*
|
|
* X = ((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog wrapper for o2111a with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a_4 (
|
|
X ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2111a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111a_4 (
|
|
X ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output X ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2111a base (
|
|
.X(X),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111A_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_V
|
|
`define SKY130_FD_SC_HD__O2111AI_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out ;
|
|
wire nand0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out , A2, A1 );
|
|
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
|
|
buf buf0 (Y , nand0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_1_V
|
|
`define SKY130_FD_SC_HD__O2111AI_1_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog wrapper for o2111ai with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai_1 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2111ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai_1 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2111ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_2_V
|
|
`define SKY130_FD_SC_HD__O2111AI_2_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog wrapper for o2111ai with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai_2 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2111ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai_2 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2111ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__O2111AI_4_V
|
|
`define SKY130_FD_SC_HD__O2111AI_4_V
|
|
|
|
/**
|
|
* o2111ai: 2-input OR into first input of 4-input NAND.
|
|
*
|
|
* Y = !((A1 | A2) & B1 & C1 & D1)
|
|
*
|
|
* Verilog wrapper for o2111ai with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai_4 (
|
|
Y ,
|
|
A1 ,
|
|
A2 ,
|
|
B1 ,
|
|
C1 ,
|
|
D1 ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A1 ;
|
|
input A2 ;
|
|
input B1 ;
|
|
input C1 ;
|
|
input D1 ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__o2111ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__o2111ai_4 (
|
|
Y ,
|
|
A1,
|
|
A2,
|
|
B1,
|
|
C1,
|
|
D1
|
|
);
|
|
|
|
output Y ;
|
|
input A1;
|
|
input A2;
|
|
input B1;
|
|
input C1;
|
|
input D1;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__o2111ai base (
|
|
.Y(Y),
|
|
.A1(A1),
|
|
.A2(A2),
|
|
.B1(B1),
|
|
.C1(C1),
|
|
.D1(D1)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__O2111AI_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_V
|
|
`define SKY130_FD_SC_HD__OR2_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, B, A );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, B, A );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_0_V
|
|
`define SKY130_FD_SC_HD__OR2_0_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog wrapper for or2 with size of 0 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_0 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_0 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_0_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_1_V
|
|
`define SKY130_FD_SC_HD__OR2_1_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog wrapper for or2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_1 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_2_V
|
|
`define SKY130_FD_SC_HD__OR2_2_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog wrapper for or2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2_4_V
|
|
`define SKY130_FD_SC_HD__OR2_4_V
|
|
|
|
/**
|
|
* or2: 2-input OR.
|
|
*
|
|
* Verilog wrapper for or2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2_4 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_V
|
|
`define SKY130_FD_SC_HD__OR2B_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b (
|
|
X ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B_N );
|
|
or or0 (or0_out_X , not0_out, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b (
|
|
X ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B_N );
|
|
or or0 (or0_out_X , not0_out, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b (
|
|
X ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B_N );
|
|
or or0 (or0_out_X, not0_out, A );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b (
|
|
X ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , B_N );
|
|
or or0 (or0_out_X, not0_out, A );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_1_V
|
|
`define SKY130_FD_SC_HD__OR2B_1_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or2b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b_1 (
|
|
X ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B_N(B_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b_1 (
|
|
X ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B_N(B_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_2_V
|
|
`define SKY130_FD_SC_HD__OR2B_2_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or2b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b_2 (
|
|
X ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B_N(B_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b_2 (
|
|
X ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B_N(B_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR2B_4_V
|
|
`define SKY130_FD_SC_HD__OR2B_4_V
|
|
|
|
/**
|
|
* or2b: 2-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or2b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b_4 (
|
|
X ,
|
|
A ,
|
|
B_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or2b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B_N(B_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or2b_4 (
|
|
X ,
|
|
A ,
|
|
B_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or2b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B_N(B_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR2B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_V
|
|
`define SKY130_FD_SC_HD__OR3_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X , B, A, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X , B, A, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, B, A, C );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, B, A, C );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_1_V
|
|
`define SKY130_FD_SC_HD__OR3_1_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog wrapper for or3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_2_V
|
|
`define SKY130_FD_SC_HD__OR3_2_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog wrapper for or3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3_4_V
|
|
`define SKY130_FD_SC_HD__OR3_4_V
|
|
|
|
/**
|
|
* or3: 3-input OR.
|
|
*
|
|
* Verilog wrapper for or3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_V
|
|
`define SKY130_FD_SC_HD__OR3B_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , C_N );
|
|
or or0 (or0_out_X , B, A, not0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , C_N );
|
|
or or0 (or0_out_X , B, A, not0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , C_N );
|
|
or or0 (or0_out_X, B, A, not0_out );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , C_N );
|
|
or or0 (or0_out_X, B, A, not0_out );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_1_V
|
|
`define SKY130_FD_SC_HD__OR3B_1_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or3b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or3b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or3b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_2_V
|
|
`define SKY130_FD_SC_HD__OR3B_2_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or3b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or3b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or3b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR3B_4_V
|
|
`define SKY130_FD_SC_HD__OR3B_4_V
|
|
|
|
/**
|
|
* or3b: 3-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or3b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or3b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or3b_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or3b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR3B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_V
|
|
`define SKY130_FD_SC_HD__OR4_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X , D, C, B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X , D, C, B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, D, C, B, A );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
or or0 (or0_out_X, D, C, B, A );
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_1_V
|
|
`define SKY130_FD_SC_HD__OR4_1_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog wrapper for or4 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_2_V
|
|
`define SKY130_FD_SC_HD__OR4_2_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog wrapper for or4 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4_4_V
|
|
`define SKY130_FD_SC_HD__OR4_4_V
|
|
|
|
/**
|
|
* or4: 4-input OR.
|
|
*
|
|
* Verilog wrapper for or4 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C,
|
|
D
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
input D;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D(D)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_V
|
|
`define SKY130_FD_SC_HD__OR4B_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
or or0 (or0_out_X , not0_out, C, B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
or or0 (or0_out_X , not0_out, C, B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
or or0 (or0_out_X, not0_out, C, B, A);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire not0_out ;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (not0_out , D_N );
|
|
or or0 (or0_out_X, not0_out, C, B, A);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_1_V
|
|
`define SKY130_FD_SC_HD__OR4B_1_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or4b with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_2_V
|
|
`define SKY130_FD_SC_HD__OR4B_2_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or4b with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4B_4_V
|
|
`define SKY130_FD_SC_HD__OR4B_4_V
|
|
|
|
/**
|
|
* or4b: 4-input OR, first input inverted.
|
|
*
|
|
* Verilog wrapper for or4b with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4b_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
D_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4b base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4B_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_V
|
|
`define SKY130_FD_SC_HD__OR4BB_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , D_N, C_N );
|
|
or or0 (or0_out_X , B, A, nand0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out ;
|
|
wire or0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out , D_N, C_N );
|
|
or or0 (or0_out_X , B, A, nand0_out );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Local signals
|
|
wire nand0_out;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out, D_N, C_N );
|
|
or or0 (or0_out_X, B, A, nand0_out);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire nand0_out;
|
|
wire or0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
nand nand0 (nand0_out, D_N, C_N );
|
|
or or0 (or0_out_X, B, A, nand0_out);
|
|
buf buf0 (X , or0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_1_V
|
|
`define SKY130_FD_SC_HD__OR4BB_1_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for or4bb with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4bb base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4bb base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_2_V
|
|
`define SKY130_FD_SC_HD__OR4BB_2_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for or4bb with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4bb base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4bb base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__OR4BB_4_V
|
|
`define SKY130_FD_SC_HD__OR4BB_4_V
|
|
|
|
/**
|
|
* or4bb: 4-input OR, first two inputs inverted.
|
|
*
|
|
* Verilog wrapper for or4bb with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N ,
|
|
D_N ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N ;
|
|
input D_N ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__or4bb base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__or4bb_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C_N,
|
|
D_N
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C_N;
|
|
input D_N;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__or4bb base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C_N(C_N),
|
|
.D_N(D_N)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__OR4BB_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBE_P_V
|
|
`define SKY130_FD_SC_HD__PROBE_P_V
|
|
|
|
/**
|
|
* probe_p: Virtual voltage probe point.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* probe_p: Virtual voltage probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probe_p (
|
|
X ,
|
|
A ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* probe_p: Virtual voltage probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probe_p (
|
|
X ,
|
|
A ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
|
|
|
|
/**
|
|
* probe_p: Virtual voltage probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probe_p (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
|
|
|
|
/**
|
|
* probe_p: Virtual voltage probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probe_p (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBE_P_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBE_P_8_V
|
|
`define SKY130_FD_SC_HD__PROBE_P_8_V
|
|
|
|
/**
|
|
* probe_p: Virtual voltage probe point.
|
|
*
|
|
* Verilog wrapper for probe_p with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probe_p_8 (
|
|
X ,
|
|
A ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
sky130_fd_sc_hd__probe_p base (
|
|
.X(X),
|
|
.A(A),
|
|
.VGND(VGND),
|
|
.VNB(VNB),
|
|
.VPB(VPB),
|
|
.VPWR(VPWR)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probe_p_8 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply0 VGND;
|
|
supply0 VNB ;
|
|
supply1 VPB ;
|
|
supply1 VPWR;
|
|
|
|
sky130_fd_sc_hd__probe_p base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBE_P_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBEC_P_V
|
|
`define SKY130_FD_SC_HD__PROBEC_P_V
|
|
|
|
/**
|
|
* probec_p: Virtual current probe point.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* probec_p: Virtual current probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probec_p (
|
|
X ,
|
|
A ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* probec_p: Virtual current probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probec_p (
|
|
X ,
|
|
A ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
|
|
// Local signals
|
|
wire buf0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X , A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
|
|
buf buf1 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
|
|
|
|
/**
|
|
* probec_p: Virtual current probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probec_p (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
|
|
|
|
/**
|
|
* probec_p: Virtual current probe point.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probec_p (
|
|
X,
|
|
A
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
buf buf0 (buf0_out_X, A );
|
|
buf buf1 (X , buf0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBEC_P_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBEC_P_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__PROBEC_P_8_V
|
|
`define SKY130_FD_SC_HD__PROBEC_P_8_V
|
|
|
|
/**
|
|
* probec_p: Virtual current probe point.
|
|
*
|
|
* Verilog wrapper for probec_p with size of 8 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probec_p_8 (
|
|
X ,
|
|
A ,
|
|
VGND,
|
|
VNB ,
|
|
VPB ,
|
|
VPWR
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input VGND;
|
|
input VNB ;
|
|
input VPB ;
|
|
input VPWR;
|
|
sky130_fd_sc_hd__probec_p base (
|
|
.X(X),
|
|
.A(A),
|
|
.VGND(VGND),
|
|
.VNB(VNB),
|
|
.VPB(VPB),
|
|
.VPWR(VPWR)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__probec_p_8 (
|
|
X,
|
|
A
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
|
|
// Voltage supply signals
|
|
supply0 VGND;
|
|
supply0 VNB ;
|
|
supply1 VPB ;
|
|
supply1 VPWR;
|
|
|
|
sky130_fd_sc_hd__probec_p base (
|
|
.X(X),
|
|
.A(A)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__PROBEC_P_8_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
not not2 (CLK , CLK_N );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire CLK_N_delayed ;
|
|
wire SET_B_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
wire cond_D ;
|
|
wire cond_SCD ;
|
|
wire cond_SCE ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
not not2 (CLK , CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
|
|
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
|
|
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
not not2 (CLK , CLK_N );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire CLK ;
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire CLK_N_delayed ;
|
|
wire SET_B_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
wire cond_D ;
|
|
wire cond_SCD ;
|
|
wire cond_SCE ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
not not2 (CLK , CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
|
|
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
|
|
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
|
|
buf buf0 (Q , buf_Q );
|
|
not not3 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_1_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_1_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfbbn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBN_2_V
|
|
`define SKY130_FD_SC_HD__SDFBBN_2_V
|
|
|
|
/**
|
|
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfbbn with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbn_2 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK_N ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK_N ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfbbn base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.CLK_N(CLK_N),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBN_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBP_V
|
|
`define SKY130_FD_SC_HD__SDFBBP_V
|
|
|
|
/**
|
|
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire CLK_delayed ;
|
|
wire SET_B_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
wire cond_D ;
|
|
wire cond_SCD ;
|
|
wire cond_SCE ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
|
|
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
|
|
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbp (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire RESET ;
|
|
wire SET ;
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire CLK_delayed ;
|
|
wire SET_B_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire mux_out ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire condb ;
|
|
wire cond_D ;
|
|
wire cond_SCD ;
|
|
wire cond_SCE ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
|
|
assign condb = ( cond0 & cond1 );
|
|
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
|
|
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
|
|
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
|
|
buf buf0 (Q , buf_Q );
|
|
not not2 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFBBP_1_V
|
|
`define SKY130_FD_SC_HD__SDFBBP_1_V
|
|
|
|
/**
|
|
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
|
|
* clock, complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfbbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfbbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.CLK(CLK),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfbbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
CLK ,
|
|
SET_B ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input CLK ;
|
|
input SET_B ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfbbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.CLK(CLK),
|
|
.SET_B(SET_B),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFBBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_1_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_1_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfrbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRBP_2_V
|
|
`define SKY130_FD_SC_HD__SDFRBP_2_V
|
|
|
|
/**
|
|
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfrbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfrbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTN_V
|
|
`define SKY130_FD_SC_HD__SDFRTN_V
|
|
|
|
/**
|
|
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intclk , CLK_N );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_N_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intclk , CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
not not1 (intclk , CLK_N );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTN_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtn (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire intclk ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_N_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
not not1 (intclk , CLK_N_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTN_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTN_1_V
|
|
`define SKY130_FD_SC_HD__SDFRTN_1_V
|
|
|
|
/**
|
|
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfrtn with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtn_1 (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfrtn base (
|
|
.Q(Q),
|
|
.CLK_N(CLK_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtn_1 (
|
|
Q ,
|
|
CLK_N ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK_N ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfrtn base (
|
|
.Q(Q),
|
|
.CLK_N(CLK_N),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTN_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (RESET , RESET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire RESET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire RESET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (RESET , RESET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_1_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_1_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfrtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_2_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_2_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfrtp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFRTP_4_V
|
|
`define SKY130_FD_SC_HD__SDFRTP_4_V
|
|
|
|
/**
|
|
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfrtp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfrtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
RESET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input RESET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfrtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.RESET_B(RESET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFRTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
not not1 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_1_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_1_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfsbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSBP_2_V
|
|
`define SKY130_FD_SC_HD__SDFSBP_2_V
|
|
|
|
/**
|
|
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfsbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfsbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfsbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
not not0 (SET , SET_B );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire SET ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed ;
|
|
wire SCE_delayed ;
|
|
wire SET_B_delayed;
|
|
wire CLK_delayed ;
|
|
wire awake ;
|
|
wire cond0 ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
wire cond4 ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (SET , SET_B_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
|
|
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_1_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_1_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfstp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_2_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_2_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfstp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFSTP_4_V
|
|
`define SKY130_FD_SC_HD__SDFSTP_4_V
|
|
|
|
/**
|
|
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sdfstp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B,
|
|
VPWR ,
|
|
VGND ,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
input VPWR ;
|
|
input VGND ;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfstp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
SET_B
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input SET_B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfstp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.SET_B(SET_B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFSTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_1_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_1_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfxbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp_1 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXBP_2_V
|
|
`define SKY130_FD_SC_HD__SDFXBP_2_V
|
|
|
|
/**
|
|
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
|
|
*
|
|
* Verilog wrapper for sdfxbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxbp_2 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
|
|
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
|
|
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_1_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_1_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog wrapper for sdfxtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp_1 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_2_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_2_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog wrapper for sdfxtp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp_2 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDFXTP_4_V
|
|
`define SKY130_FD_SC_HD__SDFXTP_4_V
|
|
|
|
/**
|
|
* sdfxtp: Scan delay flop, non-inverted clock, single output.
|
|
*
|
|
* Verilog wrapper for sdfxtp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdfxtp_4 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDFXTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire m0n ;
|
|
wire clkn ;
|
|
wire SCE_GATE;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (m0n , m0 );
|
|
not not1 (clkn , CLK );
|
|
nor nor0 (SCE_GATE, GATE, SCE );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
|
|
and and0 (GCLK , m0n, CLK );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire m0n ;
|
|
wire clkn ;
|
|
wire CLK_delayed ;
|
|
wire SCE_delayed ;
|
|
wire GATE_delayed ;
|
|
wire SCE_gate_delayed;
|
|
reg notifier ;
|
|
wire awake ;
|
|
wire SCE_awake ;
|
|
wire GATE_awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (m0n , m0 );
|
|
not not1 (clkn , CLK_delayed );
|
|
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
|
|
and and0 (GCLK , m0n, CLK_delayed );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
|
|
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire m0n ;
|
|
wire clkn ;
|
|
wire SCE_GATE;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (m0n , m0 );
|
|
not not1 (clkn , CLK );
|
|
nor nor0 (SCE_GATE, GATE, SCE );
|
|
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
|
|
and and0 (GCLK , m0n, CLK );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
// Module ports
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire m0 ;
|
|
wire m0n ;
|
|
wire clkn ;
|
|
wire CLK_delayed ;
|
|
wire SCE_delayed ;
|
|
wire GATE_delayed ;
|
|
wire SCE_gate_delayed;
|
|
reg notifier ;
|
|
wire awake ;
|
|
wire SCE_awake ;
|
|
wire GATE_awake ;
|
|
|
|
// Name Output Other arguments
|
|
not not0 (m0n , m0 );
|
|
not not1 (clkn , CLK_delayed );
|
|
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
|
|
and and0 (GCLK , m0n, CLK_delayed );
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
|
|
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_1_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_1_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog wrapper for sdlclkp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp_1 (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdlclkp base (
|
|
.GCLK(GCLK),
|
|
.SCE(SCE),
|
|
.GATE(GATE),
|
|
.CLK(CLK),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp_1 (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdlclkp base (
|
|
.GCLK(GCLK),
|
|
.SCE(SCE),
|
|
.GATE(GATE),
|
|
.CLK(CLK)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_2_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_2_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog wrapper for sdlclkp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp_2 (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdlclkp base (
|
|
.GCLK(GCLK),
|
|
.SCE(SCE),
|
|
.GATE(GATE),
|
|
.CLK(CLK),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp_2 (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdlclkp base (
|
|
.GCLK(GCLK),
|
|
.SCE(SCE),
|
|
.GATE(GATE),
|
|
.CLK(CLK)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SDLCLKP_4_V
|
|
`define SKY130_FD_SC_HD__SDLCLKP_4_V
|
|
|
|
/**
|
|
* sdlclkp: Scan gated clock.
|
|
*
|
|
* Verilog wrapper for sdlclkp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp_4 (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sdlclkp base (
|
|
.GCLK(GCLK),
|
|
.SCE(SCE),
|
|
.GATE(GATE),
|
|
.CLK(CLK),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sdlclkp_4 (
|
|
GCLK,
|
|
SCE ,
|
|
GATE,
|
|
CLK
|
|
);
|
|
|
|
output GCLK;
|
|
input SCE ;
|
|
input GATE;
|
|
input CLK ;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sdlclkp base (
|
|
.GCLK(GCLK),
|
|
.SCE(SCE),
|
|
.GATE(GATE),
|
|
.CLK(CLK)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SDLCLKP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
wire de_d ;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire de_d ;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
|
|
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
|
|
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
wire de_d ;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire de_d ;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
|
|
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
|
|
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
|
|
buf buf0 (Q , buf_Q );
|
|
not not0 (Q_N , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_1_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_1_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for sedfxbp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp_1 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sedfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp_1 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sedfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXBP_2_V
|
|
`define SKY130_FD_SC_HD__SEDFXBP_2_V
|
|
|
|
/**
|
|
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
|
|
* complementary outputs.
|
|
*
|
|
* Verilog wrapper for sedfxbp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp_2 (
|
|
Q ,
|
|
Q_N ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sedfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxbp_2 (
|
|
Q ,
|
|
Q_N,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
output Q_N;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sedfxbp base (
|
|
.Q(Q),
|
|
.Q_N(Q_N),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXBP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
wire de_d ;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire de_d ;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
|
|
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
|
|
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
wire mux_out;
|
|
wire de_d ;
|
|
|
|
// Delay Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
|
|
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
// Module ports
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire buf_Q ;
|
|
reg notifier ;
|
|
wire D_delayed ;
|
|
wire DE_delayed ;
|
|
wire SCD_delayed;
|
|
wire SCE_delayed;
|
|
wire CLK_delayed;
|
|
wire mux_out ;
|
|
wire de_d ;
|
|
wire awake ;
|
|
wire cond1 ;
|
|
wire cond2 ;
|
|
wire cond3 ;
|
|
|
|
// Name Output Other arguments
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
|
|
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
|
|
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
|
|
assign awake = ( VPWR === 1'b1 );
|
|
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
|
|
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
|
|
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
|
|
buf buf0 (Q , buf_Q );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_1_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_1_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sedfxtp with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp_1 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sedfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp_1 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sedfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_2_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_2_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sedfxtp with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp_2 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sedfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp_2 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sedfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__SEDFXTP_4_V
|
|
`define SKY130_FD_SC_HD__SEDFXTP_4_V
|
|
|
|
/**
|
|
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
|
|
* single output.
|
|
*
|
|
* Verilog wrapper for sedfxtp with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp_4 (
|
|
Q ,
|
|
CLK ,
|
|
D ,
|
|
DE ,
|
|
SCD ,
|
|
SCE ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Q ;
|
|
input CLK ;
|
|
input D ;
|
|
input DE ;
|
|
input SCD ;
|
|
input SCE ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__sedfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__sedfxtp_4 (
|
|
Q ,
|
|
CLK,
|
|
D ,
|
|
DE ,
|
|
SCD,
|
|
SCE
|
|
);
|
|
|
|
output Q ;
|
|
input CLK;
|
|
input D ;
|
|
input DE ;
|
|
input SCD;
|
|
input SCE;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__sedfxtp base (
|
|
.Q(Q),
|
|
.CLK(CLK),
|
|
.D(D),
|
|
.DE(DE),
|
|
.SCD(SCD),
|
|
.SCE(SCE)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__SEDFXTP_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_V
|
|
`define SKY130_FD_SC_HD__TAP_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap ();
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_1_V
|
|
`define SKY130_FD_SC_HD__TAP_1_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog wrapper for tap with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap_1 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__tap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap_1 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__tap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAP_2_V
|
|
`define SKY130_FD_SC_HD__TAP_2_V
|
|
|
|
/**
|
|
* tap: Tap cell with no tap connections (no contacts on metal1).
|
|
*
|
|
* Verilog wrapper for tap with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap_2 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__tap base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tap_2 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__tap base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAP_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND2_V
|
|
`define SKY130_FD_SC_HD__TAPVGND2_V
|
|
|
|
/**
|
|
* tapvgnd2: Tap cell with tap to ground, isolated power connection
|
|
* 2 rows down.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
|
|
* rows down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd2 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
|
|
* rows down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd2 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
|
|
* rows down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd2 ();
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
|
|
* rows down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd2 ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND2_1_V
|
|
`define SKY130_FD_SC_HD__TAPVGND2_1_V
|
|
|
|
/**
|
|
* tapvgnd2: Tap cell with tap to ground, isolated power connection
|
|
* 2 rows down.
|
|
*
|
|
* Verilog wrapper for tapvgnd2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd2_1 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__tapvgnd2 base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd2_1 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__tapvgnd2 base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND_V
|
|
`define SKY130_FD_SC_HD__TAPVGND_V
|
|
|
|
/**
|
|
* tapvgnd: Tap cell with tap to ground, isolated power connection
|
|
* 1 row down.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
|
|
* row down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
|
|
* row down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
|
|
|
|
/**
|
|
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
|
|
* row down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd ();
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
|
|
|
|
/**
|
|
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
|
|
* row down.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVGND_1_V
|
|
`define SKY130_FD_SC_HD__TAPVGND_1_V
|
|
|
|
/**
|
|
* tapvgnd: Tap cell with tap to ground, isolated power connection
|
|
* 1 row down.
|
|
*
|
|
* Verilog wrapper for tapvgnd with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd_1 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__tapvgnd base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvgnd_1 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__tapvgnd base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVGND_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_V
|
|
`define SKY130_FD_SC_HD__TAPVPWRVGND_V
|
|
|
|
/**
|
|
* tapvpwrvgnd: Substrate and well tap cell.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* tapvpwrvgnd: Substrate and well tap cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvpwrvgnd (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* tapvpwrvgnd: Substrate and well tap cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvpwrvgnd (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
|
|
|
|
/**
|
|
* tapvpwrvgnd: Substrate and well tap cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvpwrvgnd ();
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
|
|
|
|
/**
|
|
* tapvpwrvgnd: Substrate and well tap cell.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvpwrvgnd ();
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
// No contents.
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_1_V
|
|
`define SKY130_FD_SC_HD__TAPVPWRVGND_1_V
|
|
|
|
/**
|
|
* tapvpwrvgnd: Substrate and well tap cell.
|
|
*
|
|
* Verilog wrapper for tapvpwrvgnd with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvpwrvgnd_1 (
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__tapvpwrvgnd base (
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__tapvpwrvgnd base ();
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_V
|
|
`define SKY130_FD_SC_HD__XNOR2_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xnor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_Y , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xnor0_out_Y ;
|
|
wire pwrgood_pp0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_Y , A, B );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
|
|
buf buf0 (Y , pwrgood_pp0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Local signals
|
|
wire xnor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_Y, A, B );
|
|
buf buf0 (Y , xnor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire xnor0_out_Y;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_Y, A, B );
|
|
buf buf0 (Y , xnor0_out_Y );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_1_V
|
|
`define SKY130_FD_SC_HD__XNOR2_1_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog wrapper for xnor2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2_1 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xnor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2_1 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xnor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_2_V
|
|
`define SKY130_FD_SC_HD__XNOR2_2_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog wrapper for xnor2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2_2 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xnor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2_2 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xnor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR2_4_V
|
|
`define SKY130_FD_SC_HD__XNOR2_4_V
|
|
|
|
/**
|
|
* xnor2: 2-input exclusive NOR.
|
|
*
|
|
* Y = !(A ^ B)
|
|
*
|
|
* Verilog wrapper for xnor2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2_4 (
|
|
Y ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output Y ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xnor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor2_4 (
|
|
Y,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output Y;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xnor2 base (
|
|
.Y(Y),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_V
|
|
`define SKY130_FD_SC_HD__XNOR3_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xnor0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_X , A, B, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xnor0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_X , A, B, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire xnor0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_X, A, B, C );
|
|
buf buf0 (X , xnor0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire xnor0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xnor xnor0 (xnor0_out_X, A, B, C );
|
|
buf buf0 (X , xnor0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_1_V
|
|
`define SKY130_FD_SC_HD__XNOR3_1_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog wrapper for xnor3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xnor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xnor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_2_V
|
|
`define SKY130_FD_SC_HD__XNOR3_2_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog wrapper for xnor3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xnor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xnor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XNOR3_4_V
|
|
`define SKY130_FD_SC_HD__XNOR3_4_V
|
|
|
|
/**
|
|
* xnor3: 3-input exclusive NOR.
|
|
*
|
|
* Verilog wrapper for xnor3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xnor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xnor3_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xnor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XNOR3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_V
|
|
`define SKY130_FD_SC_HD__XOR2_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X , B, A );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Local signals
|
|
wire xor0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X, B, A );
|
|
buf buf0 (X , xor0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X, B, A );
|
|
buf buf0 (X , xor0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_1_V
|
|
`define SKY130_FD_SC_HD__XOR2_1_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog wrapper for xor2 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xor2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2_1 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xor2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_2_V
|
|
`define SKY130_FD_SC_HD__XOR2_2_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog wrapper for xor2 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xor2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2_2 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xor2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR2_4_V
|
|
`define SKY130_FD_SC_HD__XOR2_4_V
|
|
|
|
/**
|
|
* xor2: 2-input exclusive OR.
|
|
*
|
|
* X = A ^ B
|
|
*
|
|
* Verilog wrapper for xor2 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xor2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor2_4 (
|
|
X,
|
|
A,
|
|
B
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xor2 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR2_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_V
|
|
`define SKY130_FD_SC_HD__XOR3_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog top module.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
|
|
`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X , A, B, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_PP_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
|
|
`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
// Import user defined primitives.
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
// Module ports
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_X ;
|
|
wire pwrgood_pp0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X , A, B, C );
|
|
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
|
|
buf buf0 (X , pwrgood_pp0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`else // USE_POWER_PINS
|
|
|
|
`ifdef FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
|
|
`define SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Local signals
|
|
wire xor0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X, A, B, C );
|
|
buf buf0 (X , xor0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_FUNCTIONAL_V
|
|
`else // FUNCTIONAL
|
|
/*
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
|
|
`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog simulation functional model.
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
// Module ports
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Module supplies
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
// Local signals
|
|
wire xor0_out_X;
|
|
|
|
// Name Output Other arguments
|
|
xor xor0 (xor0_out_X, A, B, C );
|
|
buf buf0 (X , xor0_out_X );
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_V
|
|
`endif // FUNCTIONAL
|
|
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_1_V
|
|
`define SKY130_FD_SC_HD__XOR3_1_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog wrapper for xor3 with size of 1 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3_1 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3_1 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_1_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_2_V
|
|
`define SKY130_FD_SC_HD__XOR3_2_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog wrapper for xor3 with size of 2 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3_2 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3_2 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_2_V
|
|
|
|
|
|
//--------EOF---------
|
|
|
|
/**
|
|
* Copyright 2020 The SkyWater PDK Authors
|
|
*
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
|
* you may not use this file except in compliance with the License.
|
|
* You may obtain a copy of the License at
|
|
*
|
|
* https://www.apache.org/licenses/LICENSE-2.0
|
|
*
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
* See the License for the specific language governing permissions and
|
|
* limitations under the License.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
`ifndef SKY130_FD_SC_HD__XOR3_4_V
|
|
`define SKY130_FD_SC_HD__XOR3_4_V
|
|
|
|
/**
|
|
* xor3: 3-input exclusive OR.
|
|
*
|
|
* X = A ^ B ^ C
|
|
*
|
|
* Verilog wrapper for xor3 with size of 4 units.
|
|
*
|
|
* WARNING: This file is autogenerated, do not modify directly!
|
|
*/
|
|
|
|
`timescale 1ns / 1ps
|
|
`default_nettype none
|
|
|
|
|
|
`ifdef USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3_4 (
|
|
X ,
|
|
A ,
|
|
B ,
|
|
C ,
|
|
VPWR,
|
|
VGND,
|
|
VPB ,
|
|
VNB
|
|
);
|
|
|
|
output X ;
|
|
input A ;
|
|
input B ;
|
|
input C ;
|
|
input VPWR;
|
|
input VGND;
|
|
input VPB ;
|
|
input VNB ;
|
|
sky130_fd_sc_hd__xor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C),
|
|
.VPWR(VPWR),
|
|
.VGND(VGND),
|
|
.VPB(VPB),
|
|
.VNB(VNB)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`else // If not USE_POWER_PINS
|
|
/*********************************************************/
|
|
|
|
`celldefine
|
|
module sky130_fd_sc_hd__xor3_4 (
|
|
X,
|
|
A,
|
|
B,
|
|
C
|
|
);
|
|
|
|
output X;
|
|
input A;
|
|
input B;
|
|
input C;
|
|
|
|
// Voltage supply signals
|
|
supply1 VPWR;
|
|
supply0 VGND;
|
|
supply1 VPB ;
|
|
supply0 VNB ;
|
|
|
|
sky130_fd_sc_hd__xor3 base (
|
|
.X(X),
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
|
|
endmodule
|
|
`endcelldefine
|
|
|
|
/*********************************************************/
|
|
`endif // USE_POWER_PINS
|
|
|
|
`default_nettype wire
|
|
`endif // SKY130_FD_SC_HD__XOR3_4_V
|
|
|
|
|
|
//--------EOF---------
|
|
|