82 lines
1.6 KiB
Verilog
82 lines
1.6 KiB
Verilog
`define FUNCTIONAL
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`define UNIT_DELAY #1
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`include "sky130_hd_primitives.v"
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`include "sky130_hd.v"
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`include "gcd_sky130hd.v"
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`timescale 1 ns / 1 ps
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module gcd_tb();
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parameter clk_period = 5.0;
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parameter clk_period2 = clk_period / 2.0;
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reg clk;
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reg [15:0] a;
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reg [15:0] b;
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wire [31:0] req_msg;
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reg req_val;
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reg resp_rdy;
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reg reset;
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wire req_rdy;
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wire [15:0] resp_msg;
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wire resp_val;
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// gcd inputs share the same bus port (stoopid)
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assign req_msg[15:0] = a;
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assign req_msg[31:16] = b;
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gcd gcd1(.clk(clk), .req_msg(req_msg), .req_rdy(req_rdy), .req_val(req_val),
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.reset(reset), .resp_msg(resp_msg), .resp_rdy(resp_rdy), .resp_val(resp_val));
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initial begin
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clk = 0;
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a = 0;
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b = 0;
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req_val = 0;
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resp_rdy = 0;
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end
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always
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#clk_period2 clk = ~clk;
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initial begin
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reset = 1;
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#clk_period reset = 0;
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#clk_period a = 5; b = 10; req_val = 1;
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#clk_period req_val = 0;
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#clk_period
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#clk_period
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#clk_period
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#clk_period resp_rdy = 1;
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#clk_period resp_rdy = 0;
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#clk_period
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#clk_period a = 15; b = 150; req_val = 1;
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#clk_period req_val = 0;
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period
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#clk_period resp_rdy = 1;
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#clk_period resp_rdy = 0;
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#clk_period
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$finish;
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end
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initial
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begin
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$dumpfile("gcd_sky130hd.vcd");
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$dumpvars(0, gcd_tb);
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end
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endmodule
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