13 lines
306 B
Verilog
13 lines
306 B
Verilog
// Liberty file test: one-to-one mapping with mismatched bit widths
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// Should generate warning but still create timing arcs between bits with same index
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module liberty_arcs_one2one_2 (
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input wire [3:0] a,
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output wire [7:0] y
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);
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inv_4_to_8 partial_wide_inv_cell (
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.A(a),
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.Y(y)
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);
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endmodule |