66 lines
440 B
Plaintext
66 lines
440 B
Plaintext
[get_cells]
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r1
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r2
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r3
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u1
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u2
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[get_clocks]
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clk
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vclk
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[get_lib_cells]
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asap7_small/AND2x2_ASAP7_75t_R
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asap7_small/BUFx2_ASAP7_75t_R
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asap7_small/DFFHQx4_ASAP7_75t_R
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[get_lib_pins]
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A
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A
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B
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CLK
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D
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IQ
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IQN
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Q
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Y
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Y
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[get_libs]
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asap7_small
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[get_nets]
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clk1
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clk2
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clk3
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in1
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in2
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out
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r1q
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r2q
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u1z
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u2z
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[get_pins]
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r1/CLK
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r1/D
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r1/IQ
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r1/IQN
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r1/Q
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r2/CLK
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r2/D
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r2/IQ
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r2/IQN
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r2/Q
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r3/CLK
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r3/D
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r3/IQ
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r3/IQN
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r3/Q
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u1/A
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u1/Y
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u2/A
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u2/B
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u2/Y
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[get_ports]
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clk1
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clk2
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clk3
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in1
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in2
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out
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