43 lines
1.5 KiB
Plaintext
43 lines
1.5 KiB
Plaintext
--- report_checks ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-1.00 9.00 output external delay
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9.00 data required time
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---------------------------------------------------------
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9.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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8.92 slack (MET)
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PASS: timing analysis completed
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PASS: mock SPICE files created
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--- write_path_spice default ---
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PASS: write_path_spice default completed
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--- write_path_spice with -simulator hspice ---
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PASS: write_path_spice hspice completed
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--- write_path_spice with -simulator xyce ---
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PASS: write_path_spice xyce completed
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--- write_gate_spice ---
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INFO: write_gate_spice: invalid command name "write_gate_spice_cmd"
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PASS: write_gate_spice code path exercised
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--- write_gate_spice with -simulator hspice ---
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INFO: write_gate_spice hspice: invalid command name "write_gate_spice_cmd"
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PASS: write_gate_spice hspice code path exercised
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ALL PASSED
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