126 lines
4.0 KiB
Plaintext
126 lines
4.0 KiB
Plaintext
--- write_sdf ---
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PASS: write_sdf default
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--- write_sdf with options ---
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PASS: write_sdf with options
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--- write_sdf with digits ---
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PASS: write_sdf with digits
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--- write_sdf with include_typ ---
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PASS: write_sdf with include_typ
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--- write_timing_model ---
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PASS: write_timing_model default
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--- write_timing_model with cell_name ---
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PASS: write_timing_model with cell_name
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--- write_timing_model with library_name ---
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PASS: write_timing_model with library_name
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--- Network edit: make_instance ---
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make_instance new_buf1 done
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PASS: make_instance
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--- Network edit: make_net ---
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make_net new_net1 done
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PASS: make_net
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--- Network edit: connect_pin ---
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PASS: connect_pin
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--- Network edit: disconnect_pin ---
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Warning: search_write_sdf_model.tcl line 1, net 'new_buf1' not found.
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disconnect_pin done
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PASS: disconnect_pin
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--- Network edit: delete_net ---
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delete_net done
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PASS: delete_net
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--- Network edit: delete_instance ---
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delete_instance done
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PASS: delete_instance
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--- Network edit: replace_cell ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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replace_cell done
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PASS: replace_cell
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--- report_checks after edits ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.03 1.03 ^ and1/ZN (AND2_X1)
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0.02 1.05 ^ buf1/Z (BUF_X2)
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0.00 1.05 ^ reg1/D (DFF_X1)
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1.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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PASS: report after edits
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--- write_timing_model after edits ---
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PASS: write_timing_model after edits
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--- write_sdf after edits ---
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PASS: write_sdf after edits
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ALL PASSED
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