321 lines
9.3 KiB
Plaintext
321 lines
9.3 KiB
Plaintext
--- write_timing_model default ---
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PASS: write_timing_model default
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--- write_timing_model -cell_name ---
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PASS: write_timing_model cell_name
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--- write_timing_model -library_name -cell_name ---
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PASS: write_timing_model lib_name+cell_name
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--- write_timing_model -corner ---
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PASS: write_timing_model corner
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--- Read back generated model ---
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Warning: /workspace/sta/OpenSTA/search/test/results/timing_model_deep1.lib line 1, library search_path_end_types already exists.
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PASS: read back model
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--- min_period_violations ---
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min_period violations: 1
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PASS: min_period_violations
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--- min_period_check_slack ---
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PASS: min_period_check_slack (no check)
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--- report_min_period_checks ---
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PASS: report_min_period_checks
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--- max_skew_violations ---
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max_skew violations: 1
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PASS: max_skew_violations
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--- max_skew_check_slack ---
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PASS: max_skew_check_slack (no check)
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--- report_clock_skew -setup ---
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Clock clk
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0.00 source latency reg1/CK ^
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0.00 target latency reg2/CK ^
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0.00 CRPR
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--------------
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0.00 setup skew
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PASS: clock_skew setup
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--- report_clock_skew -hold ---
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Clock clk
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0.00 source latency reg1/CK ^
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0.00 target latency reg2/CK ^
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0.00 CRPR
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--------------
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0.00 hold skew
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PASS: clock_skew hold
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--- report_clock_skew -digits 6 ---
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Clock clk
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0.000000 source latency reg1/CK ^
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0.000000 target latency reg2/CK ^
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0.000000 CRPR
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--------------
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0.000000 setup skew
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PASS: clock_skew digits
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--- report_clock_skew -clock clk ---
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Clock clk
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0.00 source latency reg1/CK ^
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0.00 target latency reg2/CK ^
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0.00 CRPR
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--------------
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0.00 setup skew
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PASS: clock_skew named
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--- report_clock_skew -include_internal_latency ---
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Clock clk
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0.00 source latency reg1/CK ^
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0.00 target latency reg2/CK ^
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0.00 CRPR
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--------------
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0.00 setup skew
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PASS: clock_skew internal_latency
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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PASS: clock_latency
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--- report_clock_latency -include_internal_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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PASS: clock_latency internal
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--- report_clock_latency -clock clk ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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PASS: clock_latency named
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--- report_clock_latency -digits 6 ---
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Clock clk
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rise -> rise
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min max
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0.000000 0.000000 source latency
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0.000000 network latency reg1/CK
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0.000000 network latency reg1/CK
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---------------
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0.000000 0.000000 latency
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0.000000 skew
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fall -> fall
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min max
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0.000000 0.000000 source latency
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0.000000 network latency reg1/CK
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0.000000 network latency reg1/CK
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---------------
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0.000000 0.000000 latency
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0.000000 skew
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PASS: clock_latency digits
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--- report_clock_min_period ---
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clk period_min = 0.13 fmax = 7459.11
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PASS: clock_min_period
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--- report_clock_min_period -include_port_paths ---
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clk period_min = 2.12 fmax = 472.02
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PASS: clock_min_period port_paths
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--- report_clock_min_period -clocks ---
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clk period_min = 0.13 fmax = 7459.11
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PASS: clock_min_period named
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--- find_clk_min_period ---
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clk min_period: 1.34064315204796e-10
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clk min_period (with port): 2.1185453391581177e-9
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PASS: find_clk_min_period
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--- report_pulse_width_checks ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.06 5.00 4.94 (MET)
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reg2/CK (high) 0.06 5.00 4.94 (MET)
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reg1/CK (low) 0.05 5.00 4.95 (MET)
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reg2/CK (low) 0.05 5.00 4.95 (MET)
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PASS: pulse_width_checks
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--- report_pulse_width_checks -verbose ---
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.06 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.94 slack (MET)
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Pin: reg2/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg2/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg2/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.06 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.94 slack (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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5.00 open edge arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 reg1/CK
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0.00 10.00 clock reconvergence pessimism
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10.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (low)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Pin: reg2/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg2/CK
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5.00 open edge arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 reg2/CK
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0.00 10.00 clock reconvergence pessimism
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10.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (low)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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PASS: pulse_width_checks verbose
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--- min_pulse_width_checks ---
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mpw checks: 1
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PASS: min_pulse_width_checks
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--- min_pulse_width_violations ---
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mpw violations: 1
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PASS: min_pulse_width_violations
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--- min_pulse_width_check_slack ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.06 5.00 4.94 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.06 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.94 slack (MET)
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PASS: mpw slack reported
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--- max_slew_violation_count ---
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max slew violations: 0
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PASS: slew violation count
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--- max_fanout_violation_count ---
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max fanout violations: 0
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PASS: fanout violation count
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--- max_capacitance_violation_count ---
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max cap violations: 0
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PASS: cap violation count
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--- max_slew_check_slack ---
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max slew slack: 0.18774758279323578 limit: 0.1985349953174591
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PASS: slew check slack/limit
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--- max_fanout_check_slack ---
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max fanout slack: 1.0000000150474662e+30 limit: 1.0000000150474662e+30
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PASS: fanout check slack/limit
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--- max_capacitance_check_slack ---
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max cap slack: 58.474456787109375 limit: 60.577396392822266
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PASS: cap check slack/limit
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ALL PASSED
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