150 lines
5.6 KiB
Tcl
150 lines
5.6 KiB
Tcl
# Test MakeTimingModel.cc with propagated clock: findClkTreeDelays,
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# makeClkTreePaths, checkClock, makeGateModelScalar with clock tree.
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# Uses search_crpr.v which has real clock buffers.
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# Targets: MakeTimingModel.cc findClkTreeDelays, makeClkTreePaths,
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# makeGateModelScalar, checkClock, findClkedOutputPaths with clock tree,
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# makeSetupHoldTimingArcs with propagated clock,
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# findTimingFromInputs with propagated clock,
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# OutputDelays::timingSense, makeInputOutputTimingArcs
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source ../../test/helpers.tcl
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############################################################
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# Part 1: Propagated clock model with clock tree buffers
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_crpr.v
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link_design search_crpr
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create_clock -name clk -period 10 [get_ports clk]
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set_propagated_clock [get_clocks clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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# Run timing first
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report_checks -path_delay max > /dev/null
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report_checks -path_delay min > /dev/null
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puts "--- write_timing_model propagated clock ---"
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set model1 [make_result_file "model_clktree1.lib"]
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write_timing_model -library_name clktree_lib -cell_name clktree_cell $model1
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puts "PASS: write model clktree"
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puts "--- read back clktree model ---"
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read_liberty $model1
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puts "PASS: read model clktree"
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############################################################
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# Part 2: Model with clock latency + uncertainty
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_crpr.v
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link_design search_crpr
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create_clock -name clk -period 10 [get_ports clk]
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set_propagated_clock [get_clocks clk]
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set_clock_latency -source 0.5 [get_clocks clk]
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set_clock_uncertainty -setup 0.2 [get_clocks clk]
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set_clock_uncertainty -hold 0.1 [get_clocks clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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report_checks -path_delay min > /dev/null
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puts "--- write_timing_model with latency + uncertainty ---"
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set model2 [make_result_file "model_clktree2.lib"]
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write_timing_model -library_name clktree2_lib -cell_name clktree2_cell $model2
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puts "PASS: write model clktree with latency"
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puts "--- read back clktree2 model ---"
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read_liberty $model2
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puts "PASS: read model clktree2"
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############################################################
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# Part 3: Model from latch design with propagated clock
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_latch.v
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link_design search_latch
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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report_checks -path_delay min > /dev/null
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puts "--- write_timing_model latch with min/max ---"
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set model3 [make_result_file "model_clktree_latch.lib"]
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write_timing_model $model3
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puts "PASS: write model latch"
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puts "--- read back latch model ---"
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read_liberty $model3
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puts "PASS: read model latch"
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############################################################
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# Part 4: Model from multicorner design with propagated clock
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_multicorner_analysis.v
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link_design search_multicorner_analysis
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create_clock -name clk -period 8 [get_ports clk]
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set_propagated_clock [get_clocks clk]
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set_input_delay -clock clk 0.5 [get_ports in1]
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set_input_delay -clock clk 0.5 [get_ports in2]
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set_input_delay -clock clk 0.5 [get_ports in3]
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set_output_delay -clock clk 1.0 [get_ports out1]
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set_output_delay -clock clk 1.0 [get_ports out2]
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set_input_transition 0.05 [all_inputs]
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report_checks -path_delay max > /dev/null
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report_checks -path_delay min > /dev/null
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puts "--- write_timing_model multicorner propagated ---"
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set model4 [make_result_file "model_clktree_mc.lib"]
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write_timing_model -library_name mc_prop_lib -cell_name mc_prop $model4
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puts "PASS: write model multicorner propagated"
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puts "--- read back multicorner propagated model ---"
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read_liberty $model4
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puts "PASS: read model multicorner propagated"
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############################################################
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# Part 5: Model with clock transition
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_path_end_types.v
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link_design search_path_end_types
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create_clock -name clk -period 10 [get_ports clk]
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set_clock_transition 0.15 [get_clocks clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_input_delay -clock clk 0.5 [get_ports rst]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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set_output_delay -clock clk 2.0 [get_ports out3]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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puts "--- write_timing_model with clock transition ---"
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set model5 [make_result_file "model_clk_transition.lib"]
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write_timing_model -library_name ct_lib -cell_name ct_cell $model5
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puts "PASS: write model clock transition"
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puts "--- read back clock transition model ---"
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read_liberty $model5
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puts "PASS: read model clock transition"
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puts "ALL PASSED"
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