208 lines
6.6 KiB
Tcl
208 lines
6.6 KiB
Tcl
# Test additional Sta.cc and Search.cc code paths
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_test1.v
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link_design search_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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report_checks > /dev/null
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puts "--- report_path_cmd on a path ---"
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set paths [find_timing_paths -path_delay max]
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foreach pe $paths {
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set p [$pe path]
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sta::report_path_cmd $p
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break
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}
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puts "PASS: report_path_cmd"
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puts "--- report_path with json format ---"
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sta::set_report_path_format json
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set paths2 [find_timing_paths -path_delay max]
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foreach pe $paths2 {
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set p [$pe path]
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sta::report_path_cmd $p
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break
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}
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sta::set_report_path_format full
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puts "PASS: report_path json"
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puts "--- worstSlack single-arg form ---"
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catch {
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set ws [sta::worst_slack_cmd max]
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puts "worst_slack: $ws"
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}
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puts "PASS: worst_slack"
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puts "--- checkFanout via report_check_types ---"
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set_max_fanout 2 [current_design]
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report_check_types -max_fanout -verbose
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puts "PASS: checkFanout"
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puts "--- report_checks with -fields and various combos ---"
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report_checks -fields {capacitance slew fanout} -format full
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report_checks -fields {input_pin net} -format full
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report_checks -fields {capacitance slew fanout input_pin net src_attr} -format full_clock
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report_checks -fields {capacitance slew fanout input_pin net src_attr} -format full_clock_expanded
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report_checks -fields {capacitance} -format short
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report_checks -fields {slew} -format end
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puts "PASS: report_checks fields combos"
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puts "--- report_checks with -slack_min and -slack_max ---"
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report_checks -slack_max 0 -path_delay max
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report_checks -slack_min -10 -path_delay max
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report_checks -slack_max 100 -slack_min -100 -path_delay max
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puts "PASS: slack_min/max filters"
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puts "--- set_report_path_field_properties ---"
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catch { sta::set_report_path_field_properties "delay" "Delay" 10 0 }
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catch { sta::set_report_path_field_width "delay" 12 }
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report_checks -path_delay max
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puts "PASS: field properties"
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puts "--- set_report_path_sigmas ---"
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catch { sta::set_report_path_sigmas 1 }
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report_checks -path_delay max
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catch { sta::set_report_path_sigmas 0 }
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puts "PASS: report_path sigmas"
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puts "--- find_timing_paths with recovery/removal/gating_setup/gating_hold ---"
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catch {
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sta::set_recovery_removal_checks_enabled 1
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sta::set_gated_clk_checks_enabled 1
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set paths_all [find_timing_paths -path_delay max -endpoint_path_count 5 -group_path_count 5]
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puts "Paths: [llength $paths_all]"
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sta::set_recovery_removal_checks_enabled 0
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sta::set_gated_clk_checks_enabled 0
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}
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puts "PASS: recovery/gating paths"
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puts "--- report_annotated_delay ---"
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catch { report_annotated_delay }
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puts "PASS: report_annotated_delay"
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puts "--- report_annotated_check ---"
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catch { report_annotated_check }
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puts "PASS: report_annotated_check"
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puts "--- report_checks with -path_delay max_rise/max_fall/min_rise/min_fall ---"
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report_checks -path_delay max_rise -format end
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report_checks -path_delay max_fall -format end
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report_checks -path_delay min_rise -format end
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report_checks -path_delay min_fall -format end
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puts "PASS: rise/fall delay variants"
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puts "--- report_checks with -corner ---"
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set corner [sta::cmd_corner]
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report_checks -path_delay max -corner [$corner name]
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puts "PASS: report_checks corner"
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puts "--- set_report_path_no_split ---"
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sta::set_report_path_no_split 1
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report_checks -path_delay max
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sta::set_report_path_no_split 0
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puts "PASS: no_split"
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puts "--- Edge detailed methods ---"
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set edges [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
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foreach edge $edges {
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puts "sim_timing_sense: [$edge sim_timing_sense]"
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puts "cond: [$edge cond]"
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puts "mode_name: [$edge mode_name]"
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puts "mode_value: [$edge mode_value]"
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puts "is_disabled_loop: [$edge is_disabled_loop]"
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puts "is_disabled_constraint: [$edge is_disabled_constraint]"
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puts "is_disabled_constant: [$edge is_disabled_constant]"
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puts "is_disabled_cond_default: [$edge is_disabled_cond_default]"
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puts "is_disabled_bidirect_inst_path: [$edge is_disabled_bidirect_inst_path]"
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puts "is_disabled_bidirect_net_path: [$edge is_disabled_bidirect_net_path]"
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puts "is_disabled_preset_clear: [$edge is_disabled_preset_clear]"
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set dpins [$edge disabled_constant_pins]
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puts "disabled_constant_pins count: [llength $dpins]"
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set tarcs [$edge timing_arcs]
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foreach tarc $tarcs {
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set delays [$edge arc_delays $tarc]
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puts "arc_delays count: [llength $delays]"
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set dstrs [$edge arc_delay_strings $tarc 3]
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puts "arc_delay_strings count: [llength $dstrs]"
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set corner2 [sta::cmd_corner]
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puts "delay_annotated: [$edge delay_annotated $tarc $corner2 max]"
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break
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}
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break
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}
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puts "PASS: edge detailed methods"
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puts "--- Vertex methods via worst_slack_vertex ---"
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set wv [sta::worst_slack_vertex max]
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if { $wv != "NULL" } {
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puts "worst_slack_vertex is_clock: [$wv is_clock]"
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puts "worst_slack_vertex has_downstream_clk_pin: [$wv has_downstream_clk_pin]"
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puts "worst_slack_vertex is_disabled_constraint: [$wv is_disabled_constraint]"
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}
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puts "PASS: vertex methods"
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puts "--- Vertex from PathEnd ---"
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set paths_v [find_timing_paths -path_delay max]
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foreach pe $paths_v {
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set v [$pe vertex]
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puts "pathend vertex is_clock: [$v is_clock]"
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puts "pathend vertex has_downstream_clk_pin: [$v has_downstream_clk_pin]"
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break
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}
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puts "PASS: vertex from PathEnd"
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puts "--- vertex_worst_arrival_path ---"
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catch {
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set warr [sta::vertex_worst_arrival_path $wv max]
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if { $warr != "NULL" } {
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puts "worst_arrival_path pin: [get_full_name [$warr pin]]"
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}
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}
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puts "PASS: vertex_worst_arrival_path"
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puts "--- vertex_worst_slack_path ---"
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catch {
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set wslk [sta::vertex_worst_slack_path $wv max]
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if { $wslk != "NULL" } {
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puts "worst_slack_path pin: [get_full_name [$wslk pin]]"
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}
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}
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puts "PASS: vertex_worst_slack_path"
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puts "--- report_path_end with prev_end ---"
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set paths3 [find_timing_paths -path_delay max -endpoint_path_count 3]
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set prev_end ""
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foreach pe $paths3 {
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if { $prev_end != "" } {
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catch { sta::report_path_end $pe $prev_end 0 }
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}
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set prev_end $pe
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}
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puts "PASS: report_path_end with prev"
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puts "--- make_instance ---"
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catch {
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set and_cell2 [get_lib_cells NangateOpenCellLibrary/AND2_X1]
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sta::make_instance new_inst $and_cell2
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puts "make_instance: done"
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}
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puts "PASS: make_instance"
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puts "--- pocv_enabled ---"
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catch { puts "pocv_enabled: [sta::pocv_enabled]" }
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puts "PASS: pocv_enabled"
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puts "--- report_checks -summary format ---"
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report_checks -path_delay max -format summary
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puts "PASS: summary format"
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puts "--- clear_sta ---"
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catch { sta::clear_sta }
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puts "PASS: clear_sta"
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puts "ALL PASSED"
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