478 lines
17 KiB
Plaintext
478 lines
17 KiB
Plaintext
--- report_path_cmd on a path ---
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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PASS: report_path_cmd
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--- report_path with json format ---
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{
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"path": [
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/Q",
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"net": "n3",
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"arrival": 8.371e-11,
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"capacitance": 9.747e-16,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/A",
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"net": "n3",
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"arrival": 8.371e-11,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/Z",
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"net": "out1",
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"arrival": 1.003e-10,
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"capacitance": 0.000e+00,
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"slew": 3.638e-12
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},
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "out1",
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"arrival": 1.003e-10,
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"slew": 3.638e-12
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}
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]
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}
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PASS: report_path json
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--- worstSlack single-arg form ---
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worst_slack: 7.899713772019368e-9
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PASS: worst_slack
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--- checkFanout via report_check_types ---
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max fanout
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Pin and1/ZN
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max fanout 2
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fanout 1
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-----------------
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Slack 1 (MET)
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PASS: checkFanout
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--- report_checks with -fields and various combos ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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-----------------------------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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n3 (net)
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0.00 0.08 ^ buf2/A (BUF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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out1 (net)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description Src Attr
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---------------------------------------------------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1)
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n3 (net)
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0.01 0.00 0.08 ^ buf2/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1)
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out1 (net)
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0.00 0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------------------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------------------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description Src Attr
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---------------------------------------------------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg1/Q (DFF_X1)
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n3 (net)
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0.01 0.00 0.08 ^ buf2/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf2/Z (BUF_X1)
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out1 (net)
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0.00 0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------------------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------------------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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PASS: report_checks fields combos
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--- report_checks with -slack_min and -slack_max ---
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No paths found.
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: slack_min/max filters
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--- set_report_path_field_properties ---
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Warning: unknown report path field delay
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Warning: unknown report path field delay
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: field properties
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--- set_report_path_sigmas ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: report_path sigmas
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--- find_timing_paths with recovery/removal/gating_setup/gating_hold ---
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Paths: 5
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PASS: recovery/gating paths
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--- report_annotated_delay ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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PASS: report_annotated_delay
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--- report_annotated_check ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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PASS: report_annotated_check
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--- report_checks with -path_delay max_rise/max_fall/min_rise/min_fall ---
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.00 1.04 1.04 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.00 1.05 1.04 (MET)
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PASS: rise/fall delay variants
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--- report_checks with -corner ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: report_checks corner
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--- set_report_path_no_split ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: no_split
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--- Edge detailed methods ---
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sim_timing_sense: positive_unate
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cond:
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mode_name:
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mode_value:
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is_disabled_loop: 0
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is_disabled_constraint: 0
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is_disabled_constant: 0
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is_disabled_cond_default: 0
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is_disabled_bidirect_inst_path: 0
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is_disabled_bidirect_net_path: 0
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is_disabled_preset_clear: 0
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disabled_constant_pins count: 0
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arc_delays count: 2
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arc_delay_strings count: 2
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delay_annotated: 0
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PASS: edge detailed methods
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--- Vertex methods via worst_slack_vertex ---
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worst_slack_vertex is_clock: 0
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worst_slack_vertex has_downstream_clk_pin: 0
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worst_slack_vertex is_disabled_constraint: 0
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PASS: vertex methods
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--- Vertex from PathEnd ---
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pathend vertex is_clock: 0
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pathend vertex has_downstream_clk_pin: 0
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PASS: vertex from PathEnd
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--- vertex_worst_arrival_path ---
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worst_arrival_path pin: out1
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PASS: vertex_worst_arrival_path
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--- vertex_worst_slack_path ---
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worst_slack_path pin: out1
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PASS: vertex_worst_slack_path
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--- report_path_end with prev_end ---
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PASS: report_path_end with prev
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--- make_instance ---
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make_instance: done
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PASS: make_instance
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--- pocv_enabled ---
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pocv_enabled: 0
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PASS: pocv_enabled
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--- report_checks -summary format ---
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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reg1/Q (search_test1) out1 (output) 7.90
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PASS: summary format
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--- clear_sta ---
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PASS: clear_sta
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ALL PASSED
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