482 lines
15 KiB
Plaintext
482 lines
15 KiB
Plaintext
--- Ext pin cap sequence ---
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pin_load 0.01 worst_slack: 7.899686238488357e-9
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pin_load 0.05 worst_slack: 7.899576992542734e-9
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pin_load 0.1 worst_slack: 7.89943932488768e-9
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Delay Time Description
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----------------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.97 0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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----------------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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----------------------------------------------------------------
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7.90 slack (MET)
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PASS: ext pin cap sequence
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--- Ext wire cap sequence ---
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wire_load 0.01 worst_slack: 7.899686238488357e-9
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wire_load 0.05 worst_slack: 7.899576992542734e-9
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PASS: ext wire cap sequence
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--- fanout_load ---
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Warning: search_sta_bidirect_extcap.tcl line 1, set_fanout_load not supported.
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Warning: search_sta_bidirect_extcap.tcl line 1, set_fanout_load not supported.
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PASS: fanout_load
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--- port_fanout_number ---
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PASS: port_fanout_number
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--- input_transition ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: input_transition
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--- driving_cell ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: driving_cell
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--- clock_uncertainty ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.10 9.90 clock uncertainty
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0.00 9.90 clock reconvergence pessimism
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-2.00 7.90 output external delay
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7.90 data required time
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---------------------------------------------------------
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7.90 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.80 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.20 9.80 clock uncertainty
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0.00 9.80 clock reconvergence pessimism
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-2.00 7.80 output external delay
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7.80 data required time
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---------------------------------------------------------
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7.80 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.70 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.03 1.03 ^ and1/ZN (AND2_X1)
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0.02 1.05 ^ buf1/Z (BUF_X1)
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0.00 1.05 ^ reg1/D (DFF_X1)
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1.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.05 0.05 clock uncertainty
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0.00 0.05 clock reconvergence pessimism
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0.05 ^ reg1/CK (DFF_X1)
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0.00 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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0.99 slack (MET)
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PASS: clock_uncertainty
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--- report_net detail ---
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Net n1
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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buf1/A input (BUF_X1) 0.88-0.97
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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Net n3
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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reg1/Q output (DFF_X1)
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Load pins
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buf2/A input (BUF_X1) 0.88-0.97
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Warning: search_sta_bidirect_extcap.tcl line 1, report_net -connections is deprecated.
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Net n1
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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buf1/A input (BUF_X1) 0.88-0.97
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Warning: search_sta_bidirect_extcap.tcl line 1, report_net -verbose is deprecated.
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Net n1
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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buf1/A input (BUF_X1) 0.88-0.97
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Warning: search_sta_bidirect_extcap.tcl line 1, report_net -connections is deprecated.
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Warning: search_sta_bidirect_extcap.tcl line 1, report_net -verbose is deprecated.
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Net n1
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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buf1/A input (BUF_X1) 0.88-0.97
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PASS: report_net detail
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--- write_verilog ---
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PASS: write_verilog
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--- write_sdc ---
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PASS: write_sdc
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--- pocv_enabled ---
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pocv_enabled: 0
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PASS: pocv_enabled
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--- report_disabled_edges ---
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PASS: report_disabled_edges
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--- set_disable_timing on instance ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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buf1 A Z constraint
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: disable timing instance
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--- set_max_fanout ---
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max fanout
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Pin and1/ZN
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max fanout 2
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fanout 1
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-----------------
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Slack 1 (MET)
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Group Slack
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--------------------------------------------
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No paths found.
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PASS: max_fanout check_types
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--- rise/fall variants ---
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.00 1.05 1.04 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.00 1.05 1.05 (MET)
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PASS: rise/fall variants
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--- propagated clock ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (propagated)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.03 1.03 ^ and1/ZN (AND2_X1)
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0.02 1.05 ^ buf1/Z (BUF_X1)
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0.00 1.05 ^ reg1/D (DFF_X1)
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1.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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PASS: propagated clock
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--- annotated ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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PASS: annotated
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--- slow_drivers ---
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slow_drivers(4): 4
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reg1
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and1
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buf1
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buf2
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PASS: slow_drivers
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--- find_timing_paths combos ---
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1 path: 1
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5 paths: 6
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min paths: 5
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min_max paths: 6
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PASS: find_timing_paths combos
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ALL PASSED
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