705 lines
21 KiB
Plaintext
705 lines
21 KiB
Plaintext
--- isClock queries ---
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PASS: isClock
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--- ideal/propagated clock queries ---
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PASS: ideal/propagated clock
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--- sim logic values ---
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en=X clk_gate_a1=X gated=X buf1=X reg1/D=X
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PASS: sim logic values
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--- case analysis 0 on en ---
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en=0: gated_clk=0
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No paths found.
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PASS: case_analysis 0 en
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--- case analysis 1 on en ---
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en=1: gated_clk=X
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: case_analysis 1 en
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--- case analysis rising on en ---
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Startpoint: en (input port clocked by clk)
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Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
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Path Group: gated clock
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ en (in)
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0.00 1.00 ^ clk_gate/A2 (AND2_X1)
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1.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ clk_gate/A1 (AND2_X1)
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0.00 10.00 clock gating setup time
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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9.00 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: case_analysis rising en
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--- case analysis falling on en ---
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Startpoint: en (input port clocked by clk)
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Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
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Path Group: gated clock
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v en (in)
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0.00 1.00 v clk_gate/A2 (AND2_X1)
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1.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ clk_gate/A1 (AND2_X1)
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0.00 10.00 clock gating setup time
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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9.00 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: case_analysis falling en
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--- set_logic_zero ---
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in1=0: buf1/Z=0
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Startpoint: en (input port clocked by clk)
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Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
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Path Group: gated clock
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v en (in)
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0.00 1.00 v clk_gate/A2 (AND2_X1)
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1.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ clk_gate/A1 (AND2_X1)
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0.00 10.00 clock gating setup time
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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9.00 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: logic_zero
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--- set_logic_one ---
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en=1: clk_gate/A2=1
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: logic_one
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--- findLogicConstants ---
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PASS: findLogicConstants
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--- clearLogicConstants ---
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PASS: clearLogicConstants
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--- levelize ---
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PASS: levelize
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--- graphLoops ---
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PASS: graphLoops
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--- max_path_count_vertex ---
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PASS: max_path_count_vertex
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--- generated clock ---
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock gclk (rise edge)
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0.02 0.02 clock network delay
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0.02 ^ out1 (out)
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0.02 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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-2.00 -2.00 output external delay
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-2.00 data required time
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---------------------------------------------------------
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-2.00 data required time
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-0.02 data arrival time
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---------------------------------------------------------
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2.02 slack (MET)
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PASS: generated clock
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--- report_clock_properties with genclk ---
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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gclk 20.00 0.00 10.00 (generated)
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PASS: clock properties with genclk
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--- clock skew with genclk ---
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Clock clk
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No launch/capture paths found.
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Clock gclk
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No launch/capture paths found.
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Clock clk
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No launch/capture paths found.
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Clock gclk
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No launch/capture paths found.
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PASS: clock skew genclk
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--- clock min period ---
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clk period_min = 0.00 fmax = inf
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gclk period_min = 0.00 fmax = inf
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clk period_min = 0.00 fmax = inf
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gclk period_min = 0.00 fmax = inf
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PASS: clock min period
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--- clock latency report ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.02 network latency reg1/CK
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---------------
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0.02 0.02 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.02 network latency reg1/CK
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---------------
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0.02 0.02 latency
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0.00 skew
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Clock gclk
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.02 network latency reg1/CK
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---------------
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0.02 0.02 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.02 network latency reg1/CK
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---------------
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0.02 0.02 latency
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0.00 skew
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Clock gclk
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Clock clk
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rise -> rise
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min max
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0.000000 0.000000 source latency
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0.024409 network latency reg1/CK
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0.024409 network latency reg1/CK
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---------------
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0.024409 0.024409 latency
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0.000000 skew
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fall -> fall
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min max
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0.000000 0.000000 source latency
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0.022412 network latency reg1/CK
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0.022412 network latency reg1/CK
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---------------
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0.022412 0.022412 latency
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0.000000 skew
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Clock gclk
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PASS: clock latency report
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--- find_timing_paths for clock groups ---
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Max paths: 2
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pin=out1 slack=7.978649740891797e-9
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pin=out1 slack=7.983420147184006e-9
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PASS: timing paths
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--- report_checks through clock gate ---
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No paths found.
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No paths found.
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PASS: through clock gate
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--- bidirect inst paths ---
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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PASS: bidirect inst paths
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--- bidirect net paths ---
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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PASS: bidirect net paths
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--- clk thru tristate ---
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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10.02 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-2.00 18.00 output external delay
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18.00 data required time
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---------------------------------------------------------
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18.00 data required time
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-10.02 data arrival time
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---------------------------------------------------------
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7.98 slack (MET)
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PASS: clk thru tristate
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--- dynamic loop breaking ---
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Startpoint: reg1/Q (clock source 'gclk')
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock gclk (fall edge)
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0.02 10.02 clock network delay
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10.02 v out1 (out)
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|
10.02 data arrival time
|
|
|
|
20.00 20.00 clock clk (rise edge)
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|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-2.00 18.00 output external delay
|
|
18.00 data required time
|
|
---------------------------------------------------------
|
|
18.00 data required time
|
|
-10.02 data arrival time
|
|
---------------------------------------------------------
|
|
7.98 slack (MET)
|
|
|
|
|
|
Startpoint: reg1/Q (clock source 'gclk')
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock gclk (fall edge)
|
|
0.02 10.02 clock network delay
|
|
10.02 v out1 (out)
|
|
10.02 data arrival time
|
|
|
|
20.00 20.00 clock clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-2.00 18.00 output external delay
|
|
18.00 data required time
|
|
---------------------------------------------------------
|
|
18.00 data required time
|
|
-10.02 data arrival time
|
|
---------------------------------------------------------
|
|
7.98 slack (MET)
|
|
|
|
|
|
PASS: dynamic loop breaking
|
|
--- use default arrival clock ---
|
|
Startpoint: reg1/Q (clock source 'gclk')
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock gclk (fall edge)
|
|
0.02 10.02 clock network delay
|
|
10.02 v out1 (out)
|
|
10.02 data arrival time
|
|
|
|
20.00 20.00 clock clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-2.00 18.00 output external delay
|
|
18.00 data required time
|
|
---------------------------------------------------------
|
|
18.00 data required time
|
|
-10.02 data arrival time
|
|
---------------------------------------------------------
|
|
7.98 slack (MET)
|
|
|
|
|
|
Startpoint: reg1/Q (clock source 'gclk')
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock gclk (fall edge)
|
|
0.02 10.02 clock network delay
|
|
10.02 v out1 (out)
|
|
10.02 data arrival time
|
|
|
|
20.00 20.00 clock clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-2.00 18.00 output external delay
|
|
18.00 data required time
|
|
---------------------------------------------------------
|
|
18.00 data required time
|
|
-10.02 data arrival time
|
|
---------------------------------------------------------
|
|
7.98 slack (MET)
|
|
|
|
|
|
PASS: use default arrival clock
|
|
--- propagate all clocks ---
|
|
Startpoint: reg1/Q (clock source 'gclk')
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock gclk (fall edge)
|
|
0.02 10.02 clock network delay
|
|
10.02 v out1 (out)
|
|
10.02 data arrival time
|
|
|
|
20.00 20.00 clock clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-2.00 18.00 output external delay
|
|
18.00 data required time
|
|
---------------------------------------------------------
|
|
18.00 data required time
|
|
-10.02 data arrival time
|
|
---------------------------------------------------------
|
|
7.98 slack (MET)
|
|
|
|
|
|
Startpoint: reg1/Q (clock source 'gclk')
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock gclk (fall edge)
|
|
0.02 10.02 clock network delay
|
|
10.02 v out1 (out)
|
|
10.02 data arrival time
|
|
|
|
20.00 20.00 clock clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-2.00 18.00 output external delay
|
|
18.00 data required time
|
|
---------------------------------------------------------
|
|
18.00 data required time
|
|
-10.02 data arrival time
|
|
---------------------------------------------------------
|
|
7.98 slack (MET)
|
|
|
|
|
|
PASS: propagate all clocks
|
|
ALL PASSED
|