265 lines
13 KiB
Tcl
265 lines
13 KiB
Tcl
# Test Property.cc deeper: LibertyPort drive_resistance and intrinsic_delay
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# properties, Instance is_* properties, LibertyCell area/leakage properties,
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# path group matching, filterGroupPathMatches, additional timing arc set
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# property queries, and TimingArcSet full_name.
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# Targets: Property.cc getProperty for LibertyPort (drive_resistance,
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# drive_resistance_min_rise, drive_resistance_max_rise,
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# drive_resistance_min_fall, drive_resistance_max_fall,
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# intrinsic_delay, intrinsic_delay_min_rise, intrinsic_delay_max_rise,
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# intrinsic_delay_min_fall, intrinsic_delay_max_fall,
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# lib_cell, is_clock, is_register_clock, capacitance),
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# Instance (is_hierarchical, is_buffer, is_clock_gate, is_inverter,
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# is_macro, is_memory),
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# Search.cc groupPathMatches, filterGroupPathMatches,
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# PathGroup.cc matchPathEnds
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_multicorner_analysis.v
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link_design search_multicorner_analysis
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.5 [get_ports in2]
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set_input_delay -clock clk 0.8 [get_ports in3]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 1.5 [get_ports out2]
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# Force timing
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report_checks -path_delay max > /dev/null
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report_checks -path_delay min > /dev/null
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############################################################
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# LibertyPort drive_resistance properties
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############################################################
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puts "--- LibertyPort drive_resistance properties ---"
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set buf_out [get_lib_pins NangateOpenCellLibrary/BUF_X1/Z]
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puts "BUF_X1/Z drive_resistance: [get_property $buf_out drive_resistance]"
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puts "BUF_X1/Z drive_resistance_min_rise: [get_property $buf_out drive_resistance_min_rise]"
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puts "BUF_X1/Z drive_resistance_max_rise: [get_property $buf_out drive_resistance_max_rise]"
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puts "BUF_X1/Z drive_resistance_min_fall: [get_property $buf_out drive_resistance_min_fall]"
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puts "BUF_X1/Z drive_resistance_max_fall: [get_property $buf_out drive_resistance_max_fall]"
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puts "PASS: drive_resistance"
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puts "--- More drive_resistance on different cells ---"
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set and_out [get_lib_pins NangateOpenCellLibrary/AND2_X1/ZN]
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puts "AND2_X1/ZN drive_resistance: [get_property $and_out drive_resistance]"
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puts "AND2_X1/ZN drive_resistance_min_rise: [get_property $and_out drive_resistance_min_rise]"
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puts "AND2_X1/ZN drive_resistance_max_fall: [get_property $and_out drive_resistance_max_fall]"
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set inv_out [get_lib_pins NangateOpenCellLibrary/INV_X1/ZN]
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puts "INV_X1/ZN drive_resistance: [get_property $inv_out drive_resistance]"
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puts "INV_X1/ZN drive_resistance_min_rise: [get_property $inv_out drive_resistance_min_rise]"
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puts "INV_X1/ZN drive_resistance_max_fall: [get_property $inv_out drive_resistance_max_fall]"
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puts "PASS: drive_resistance multi"
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############################################################
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# LibertyPort intrinsic_delay properties
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############################################################
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puts "--- LibertyPort intrinsic_delay properties ---"
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puts "BUF_X1/Z intrinsic_delay: [get_property $buf_out intrinsic_delay]"
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puts "BUF_X1/Z intrinsic_delay_min_rise: [get_property $buf_out intrinsic_delay_min_rise]"
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puts "BUF_X1/Z intrinsic_delay_max_rise: [get_property $buf_out intrinsic_delay_max_rise]"
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puts "BUF_X1/Z intrinsic_delay_min_fall: [get_property $buf_out intrinsic_delay_min_fall]"
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puts "BUF_X1/Z intrinsic_delay_max_fall: [get_property $buf_out intrinsic_delay_max_fall]"
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puts "PASS: intrinsic_delay BUF"
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puts "--- intrinsic_delay on AND ---"
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puts "AND2_X1/ZN intrinsic_delay: [get_property $and_out intrinsic_delay]"
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puts "AND2_X1/ZN intrinsic_delay_min_rise: [get_property $and_out intrinsic_delay_min_rise]"
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puts "AND2_X1/ZN intrinsic_delay_max_rise: [get_property $and_out intrinsic_delay_max_rise]"
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puts "AND2_X1/ZN intrinsic_delay_min_fall: [get_property $and_out intrinsic_delay_min_fall]"
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puts "AND2_X1/ZN intrinsic_delay_max_fall: [get_property $and_out intrinsic_delay_max_fall]"
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puts "PASS: intrinsic_delay AND"
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puts "--- intrinsic_delay on INV ---"
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puts "INV_X1/ZN intrinsic_delay: [get_property $inv_out intrinsic_delay]"
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puts "INV_X1/ZN intrinsic_delay_min_rise: [get_property $inv_out intrinsic_delay_min_rise]"
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puts "INV_X1/ZN intrinsic_delay_max_fall: [get_property $inv_out intrinsic_delay_max_fall]"
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puts "PASS: intrinsic_delay INV"
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############################################################
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# LibertyPort lib_cell, is_clock, is_register_clock, capacitance
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############################################################
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puts "--- LibertyPort lib_cell and clock properties ---"
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set buf_in [get_lib_pins NangateOpenCellLibrary/BUF_X1/A]
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puts "BUF_X1/A capacitance: [get_property $buf_in capacitance]"
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set buf_lc [get_property $buf_in lib_cell]
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puts "BUF_X1/A lib_cell: [get_name $buf_lc]"
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puts "BUF_X1/A is_clock: [get_property $buf_in is_clock]"
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puts "BUF_X1/A is_register_clock: [get_property $buf_in is_register_clock]"
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set dff_ck [get_lib_pins NangateOpenCellLibrary/DFF_X1/CK]
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puts "DFF_X1/CK is_clock: [get_property $dff_ck is_clock]"
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puts "DFF_X1/CK is_register_clock: [get_property $dff_ck is_register_clock]"
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puts "DFF_X1/CK capacitance: [get_property $dff_ck capacitance]"
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set dff_lc [get_property $dff_ck lib_cell]
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puts "DFF_X1/CK lib_cell: [get_name $dff_lc]"
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set dff_d [get_lib_pins NangateOpenCellLibrary/DFF_X1/D]
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puts "DFF_X1/D is_clock: [get_property $dff_d is_clock]"
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puts "DFF_X1/D is_register_clock: [get_property $dff_d is_register_clock]"
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puts "DFF_X1/D capacitance: [get_property $dff_d capacitance]"
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puts "PASS: lib_cell/is_clock/capacitance"
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############################################################
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# Instance is_* properties
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############################################################
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puts "--- Instance is_* properties ---"
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set buf_inst [get_cells buf1]
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puts "buf1 is_buffer: [get_property $buf_inst is_buffer]"
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puts "buf1 is_inverter: [get_property $buf_inst is_inverter]"
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puts "buf1 is_clock_gate: [get_property $buf_inst is_clock_gate]"
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puts "buf1 is_macro: [get_property $buf_inst is_macro]"
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puts "buf1 is_memory: [get_property $buf_inst is_memory]"
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puts "buf1 is_hierarchical: [get_property $buf_inst is_hierarchical]"
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set inv_inst [get_cells inv1]
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puts "inv1 is_buffer: [get_property $inv_inst is_buffer]"
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puts "inv1 is_inverter: [get_property $inv_inst is_inverter]"
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puts "inv1 is_clock_gate: [get_property $inv_inst is_clock_gate]"
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set and_inst [get_cells and1]
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puts "and1 is_buffer: [get_property $and_inst is_buffer]"
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puts "and1 is_inverter: [get_property $and_inst is_inverter]"
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set reg_inst [get_cells reg1]
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puts "reg1 is_buffer: [get_property $reg_inst is_buffer]"
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puts "reg1 is_inverter: [get_property $reg_inst is_inverter]"
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puts "reg1 is_macro: [get_property $reg_inst is_macro]"
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puts "reg1 is_memory: [get_property $reg_inst is_memory]"
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puts "PASS: instance is_* properties"
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############################################################
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# LibertyCell area and leakage power
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############################################################
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puts "--- LibertyCell area and leakage ---"
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set dff_cell [get_lib_cells NangateOpenCellLibrary/DFF_X1]
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catch { puts "DFF_X1 area: [get_property $dff_cell area]" }
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catch { puts "DFF_X1 cell_leakage_power: [get_property $dff_cell cell_leakage_power]" }
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set buf_cell [get_lib_cells NangateOpenCellLibrary/BUF_X1]
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catch { puts "BUF_X1 area: [get_property $buf_cell area]" }
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catch { puts "BUF_X1 cell_leakage_power: [get_property $buf_cell cell_leakage_power]" }
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set inv_cell [get_lib_cells NangateOpenCellLibrary/INV_X1]
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catch { puts "INV_X1 area: [get_property $inv_cell area]" }
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set and_cell [get_lib_cells NangateOpenCellLibrary/AND2_X1]
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catch { puts "AND2_X1 area: [get_property $and_cell area]" }
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puts "PASS: cell area/leakage"
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############################################################
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# Path group matching: group_path -name with -from and -through
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# This exercises Search.cc groupPathMatches, filterGroupPathMatches
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############################################################
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puts "--- group_path matching ---"
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group_path -name input_grp -from [get_ports {in1 in2 in3}]
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group_path -name reg2reg_grp -from [get_pins reg1/CK] -to [get_pins reg2/D]
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group_path -name output_grp -to [get_ports {out1 out2}]
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group_path -name through_grp -through [get_pins inv1/ZN]
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puts "--- report_checks with groups ---"
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report_checks -path_delay max
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puts "PASS: report_checks with groups"
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puts "--- find_timing_paths with group_path ---"
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set paths [find_timing_paths -path_delay max -group_path_count 20 -endpoint_path_count 10]
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puts "Found [llength $paths] paths with groups"
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foreach pe $paths {
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catch {
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set pg [$pe path_group]
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puts " [get_full_name [$pe pin]] group=[$pg name] slack=[$pe slack]"
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}
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}
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puts "PASS: paths with groups"
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puts "--- find_timing_paths with min paths and groups ---"
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set paths_min [find_timing_paths -path_delay min -group_path_count 20 -endpoint_path_count 10]
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puts "Found [llength $paths_min] min paths with groups"
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foreach pe $paths_min {
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catch {
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set pg [$pe path_group]
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puts " [get_full_name [$pe pin]] group=[$pg name] slack=[$pe slack]"
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}
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}
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puts "PASS: min paths with groups"
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############################################################
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# path_group_names and is_path_group_name
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############################################################
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puts "--- path_group_names ---"
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set group_names [sta::path_group_names]
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puts "Path group names: $group_names"
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catch { puts "input_grp is group: [sta::is_path_group_name input_grp]" }
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catch { puts "nonexistent is group: [sta::is_path_group_name nonexistent_grp]" }
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puts "PASS: path_group_names"
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############################################################
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# TimingArcSet properties on different cell types
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############################################################
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puts "--- TimingArcSet properties on DFF_X1 ---"
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set dff_cell2 [get_lib_cells NangateOpenCellLibrary/DFF_X1]
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set arcsets [$dff_cell2 timing_arc_sets]
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foreach arcset $arcsets {
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set arcname [sta::timing_arc_property $arcset full_name]
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set arcname2 [sta::timing_arc_property $arcset name]
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puts "DFF_X1 arc: $arcname / $arcname2"
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}
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puts "PASS: DFF_X1 arc set properties"
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puts "--- TimingArcSet properties on DFFR_X1 ---"
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set dffr_cell [get_lib_cells NangateOpenCellLibrary/DFFR_X1]
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set arcsets_r [$dffr_cell timing_arc_sets]
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foreach arcset $arcsets_r {
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set arcname [sta::timing_arc_property $arcset full_name]
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puts "DFFR_X1 arc: $arcname"
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}
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puts "PASS: DFFR_X1 arc set properties"
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puts "--- TimingArcSet properties on OR2_X1 ---"
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set or_cell [get_lib_cells NangateOpenCellLibrary/OR2_X1]
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set arcsets_o [$or_cell timing_arc_sets]
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foreach arcset $arcsets_o {
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set arcname [sta::timing_arc_property $arcset full_name]
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set arcname2 [sta::timing_arc_property $arcset name]
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puts "OR2_X1 arc: $arcname / $arcname2"
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}
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puts "PASS: OR2_X1 arc set properties"
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############################################################
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# Pin property: is_hierarchical, is_port
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############################################################
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puts "--- Pin is_hierarchical/is_port ---"
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set p1 [get_pins reg1/D]
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puts "reg1/D is_hierarchical: [get_property $p1 is_hierarchical]"
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puts "reg1/D is_port: [get_property $p1 is_port]"
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puts "PASS: pin is_hierarchical/is_port"
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############################################################
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# LibertyPort direction on different port types
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############################################################
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puts "--- LibertyPort direction varieties ---"
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set dff_q [get_lib_pins NangateOpenCellLibrary/DFF_X1/Q]
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puts "DFF_X1/Q direction: [get_property $dff_q direction]"
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set dff_d_lp [get_lib_pins NangateOpenCellLibrary/DFF_X1/D]
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puts "DFF_X1/D direction: [get_property $dff_d_lp direction]"
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set dff_ck_lp [get_lib_pins NangateOpenCellLibrary/DFF_X1/CK]
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puts "DFF_X1/CK direction: [get_property $dff_ck_lp direction]"
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puts "PASS: liberty port directions"
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############################################################
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# Unknown property error handling for various types
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############################################################
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puts "--- Unknown property errors ---"
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catch { get_property [get_lib_pins NangateOpenCellLibrary/BUF_X1/Z] nonexistent_prop } err1
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puts "LibertyPort unknown: [string range $err1 0 40]"
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catch { get_property [get_cells reg1] nonexistent_prop } err2
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puts "Instance unknown: [string range $err2 0 40]"
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catch { get_property [get_clocks clk] nonexistent_prop } err3
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puts "Clock unknown: [string range $err3 0 40]"
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catch { get_property [get_lib_cells NangateOpenCellLibrary/BUF_X1] nonexistent_prop } err4
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puts "LibertyCell unknown: [string range $err4 0 40]"
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catch { get_property [get_libs NangateOpenCellLibrary] nonexistent_prop } err5
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puts "Library unknown: [string range $err5 0 40]"
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puts "PASS: unknown property errors"
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puts "ALL PASSED"
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