249 lines
8.3 KiB
Plaintext
249 lines
8.3 KiB
Plaintext
--- LibertyPort drive_resistance properties ---
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BUF_X1/Z drive_resistance: 2.327937
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BUF_X1/Z drive_resistance_min_rise: 2.327937
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BUF_X1/Z drive_resistance_max_rise: 2.327937
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BUF_X1/Z drive_resistance_min_fall: 1.083897
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BUF_X1/Z drive_resistance_max_fall: 1.083897
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PASS: drive_resistance
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--- More drive_resistance on different cells ---
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AND2_X1/ZN drive_resistance: 2.333555
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AND2_X1/ZN drive_resistance_min_rise: 2.333449
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AND2_X1/ZN drive_resistance_max_fall: 1.085789
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INV_X1/ZN drive_resistance: 2.322186
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INV_X1/ZN drive_resistance_min_rise: 2.322186
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INV_X1/ZN drive_resistance_max_fall: 1.071745
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PASS: drive_resistance multi
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--- LibertyPort intrinsic_delay properties ---
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BUF_X1/Z intrinsic_delay: 0.018876
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BUF_X1/Z intrinsic_delay_min_rise: 0.013565
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BUF_X1/Z intrinsic_delay_max_rise: 0.013565
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BUF_X1/Z intrinsic_delay_min_fall: 0.018876
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BUF_X1/Z intrinsic_delay_max_fall: 0.018876
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PASS: intrinsic_delay BUF
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--- intrinsic_delay on AND ---
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AND2_X1/ZN intrinsic_delay: 0.022618
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AND2_X1/ZN intrinsic_delay_min_rise: 0.021327
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AND2_X1/ZN intrinsic_delay_max_rise: 0.022618
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AND2_X1/ZN intrinsic_delay_min_fall: 0.020427
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AND2_X1/ZN intrinsic_delay_max_fall: 0.022613
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PASS: intrinsic_delay AND
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--- intrinsic_delay on INV ---
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INV_X1/ZN intrinsic_delay: 0.004075
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INV_X1/ZN intrinsic_delay_min_rise: 0.004075
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INV_X1/ZN intrinsic_delay_max_fall: 0.002482
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PASS: intrinsic_delay INV
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--- LibertyPort lib_cell and clock properties ---
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BUF_X1/A capacitance: 0.974659
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BUF_X1/A lib_cell: BUF_X1
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BUF_X1/A is_clock: 0
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BUF_X1/A is_register_clock: 0
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DFF_X1/CK is_clock: 1
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DFF_X1/CK is_register_clock: 1
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DFF_X1/CK capacitance: 0.949653
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DFF_X1/CK lib_cell: DFF_X1
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DFF_X1/D is_clock: 0
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DFF_X1/D is_register_clock: 0
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DFF_X1/D capacitance: 1.140290
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PASS: lib_cell/is_clock/capacitance
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--- Instance is_* properties ---
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buf1 is_buffer: 1
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buf1 is_inverter: 0
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buf1 is_clock_gate: 0
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buf1 is_macro: 0
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buf1 is_memory: 0
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buf1 is_hierarchical: 0
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inv1 is_buffer: 0
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inv1 is_inverter: 1
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inv1 is_clock_gate: 0
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and1 is_buffer: 0
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and1 is_inverter: 0
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reg1 is_buffer: 0
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reg1 is_inverter: 0
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reg1 is_macro: 0
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reg1 is_memory: 0
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PASS: instance is_* properties
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--- LibertyCell area and leakage ---
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DFF_X1 area: 4.522000
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BUF_X1 area: 0.798000
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INV_X1 area: 0.532000
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AND2_X1 area: 1.064000
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PASS: cell area/leakage
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--- group_path matching ---
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--- report_checks with groups ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: input_grp
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.50 1.50 v input external delay
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0.00 1.50 v in2 (in)
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0.02 1.52 v and1/ZN (AND2_X1)
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0.04 1.57 v or1/ZN (OR2_X1)
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0.03 1.59 v buf1/Z (BUF_X1)
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0.01 1.60 ^ inv1/ZN (INV_X1)
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0.02 1.62 ^ buf2/Z (BUF_X2)
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0.00 1.62 ^ reg1/D (DFF_X1)
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1.62 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.62 data arrival time
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---------------------------------------------------------
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8.35 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: output_grp
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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7.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: reg2reg_grp
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.03 0.11 v buf3/Z (BUF_X1)
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0.00 0.11 v reg2/D (DFF_X1)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.85 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: through_grp
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.50 1.50 v input external delay
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0.00 1.50 v in2 (in)
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0.02 1.52 v and1/ZN (AND2_X1)
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0.04 1.57 v or1/ZN (OR2_X1)
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0.03 1.59 v buf1/Z (BUF_X1)
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0.01 1.60 ^ inv1/ZN (INV_X1)
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0.02 1.62 ^ buf2/Z (BUF_X2)
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0.00 1.62 ^ reg1/D (DFF_X1)
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1.62 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.62 data arrival time
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---------------------------------------------------------
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8.35 slack (MET)
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PASS: report_checks with groups
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--- find_timing_paths with group_path ---
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Found 18 paths with groups
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PASS: paths with groups
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--- find_timing_paths with min paths and groups ---
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Found 18 min paths with groups
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PASS: min paths with groups
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--- path_group_names ---
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Path group names: clk input_grp output_grp reg2reg_grp through_grp asynchronous {path delay} {gated clock} unconstrained
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input_grp is group: 1
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nonexistent is group: 0
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PASS: path_group_names
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--- TimingArcSet properties on DFF_X1 ---
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DFF_X1 arc: DFF_X1 CK -> D / DFF_X1 CK -> D
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DFF_X1 arc: DFF_X1 CK -> D / DFF_X1 CK -> D
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DFF_X1 arc: DFF_X1 CK -> CK / DFF_X1 CK -> CK
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DFF_X1 arc: DFF_X1 CK -> Q / DFF_X1 CK -> Q
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DFF_X1 arc: DFF_X1 CK -> QN / DFF_X1 CK -> QN
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PASS: DFF_X1 arc set properties
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--- TimingArcSet properties on DFFR_X1 ---
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DFFR_X1 arc: DFFR_X1 CK -> D
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DFFR_X1 arc: DFFR_X1 CK -> D
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DFFR_X1 arc: DFFR_X1 CK -> RN
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DFFR_X1 arc: DFFR_X1 CK -> RN
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DFFR_X1 arc: DFFR_X1 RN -> RN
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DFFR_X1 arc: DFFR_X1 CK -> CK
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DFFR_X1 arc: DFFR_X1 CK -> Q
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DFFR_X1 arc: DFFR_X1 RN -> Q
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DFFR_X1 arc: DFFR_X1 RN -> Q
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DFFR_X1 arc: DFFR_X1 RN -> Q
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DFFR_X1 arc: DFFR_X1 RN -> Q
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DFFR_X1 arc: DFFR_X1 CK -> QN
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DFFR_X1 arc: DFFR_X1 RN -> QN
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DFFR_X1 arc: DFFR_X1 RN -> QN
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DFFR_X1 arc: DFFR_X1 RN -> QN
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DFFR_X1 arc: DFFR_X1 RN -> QN
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PASS: DFFR_X1 arc set properties
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--- TimingArcSet properties on OR2_X1 ---
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OR2_X1 arc: OR2_X1 A1 -> ZN / OR2_X1 A1 -> ZN
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OR2_X1 arc: OR2_X1 A2 -> ZN / OR2_X1 A2 -> ZN
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PASS: OR2_X1 arc set properties
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--- Pin is_hierarchical/is_port ---
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reg1/D is_hierarchical: 0
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reg1/D is_port: 0
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PASS: pin is_hierarchical/is_port
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--- LibertyPort direction varieties ---
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DFF_X1/Q direction: output
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DFF_X1/D direction: input
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DFF_X1/CK direction: input
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PASS: liberty port directions
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--- Unknown property errors ---
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LibertyPort unknown: Error: liberty_port objects do not have a
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Instance unknown: Error: instance objects do not have a non
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Clock unknown: Error: clock objects do not have a nonexi
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LibertyCell unknown: Error: liberty_cell objects do not have a
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Library unknown: Error: liberty_library objects do not hav
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PASS: unknown property errors
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ALL PASSED
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