275 lines
12 KiB
Tcl
275 lines
12 KiB
Tcl
# Test Property.cc: instance properties (is_buffer, is_inverter, is_macro,
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# is_memory, is_clock_gate, is_hierarchical, liberty_cell, cell),
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# LibertyCell properties (is_inverter, is_memory, dont_use, area),
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# Pin properties (is_port, is_hierarchical, direction, pin_direction),
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# Net properties, Port properties (liberty_port, activity, slack/slew variants),
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# PathEnd property "points", Clock property "is_propagated",
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# LibertyLibrary property "filename",
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# Cell property full_name/library/filename.
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# Targets: Property.cc getProperty for Instance, LibertyCell, Pin, Net, Port,
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# Cell, LibertyLibrary, Clock (is_propagated), PathEnd (points).
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_test1.v
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link_design search_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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# Run timing so arrivals/requireds are computed
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report_checks -path_delay max > /dev/null
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report_checks -path_delay min > /dev/null
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############################################################
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# Instance properties: is_buffer, is_inverter, is_clock_gate,
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# is_macro, is_memory, is_hierarchical,
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# liberty_cell, cell
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############################################################
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puts "--- Instance is_buffer/is_inverter ---"
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set buf_inst [get_cells buf1]
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puts "buf1 is_buffer: [get_property $buf_inst is_buffer]"
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puts "buf1 is_inverter: [get_property $buf_inst is_inverter]"
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puts "buf1 is_clock_gate: [get_property $buf_inst is_clock_gate]"
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puts "buf1 is_macro: [get_property $buf_inst is_macro]"
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puts "buf1 is_memory: [get_property $buf_inst is_memory]"
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puts "buf1 is_hierarchical: [get_property $buf_inst is_hierarchical]"
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set buf_lc [get_property $buf_inst liberty_cell]
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puts "buf1 liberty_cell: [get_name $buf_lc]"
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set buf_cell [get_property $buf_inst cell]
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puts "buf1 cell: [get_name $buf_cell]"
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puts "PASS: instance properties"
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puts "--- Instance properties for and gate ---"
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set and_inst [get_cells and1]
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puts "and1 is_buffer: [get_property $and_inst is_buffer]"
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puts "and1 is_inverter: [get_property $and_inst is_inverter]"
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puts "and1 is_clock_gate: [get_property $and_inst is_clock_gate]"
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puts "and1 is_macro: [get_property $and_inst is_macro]"
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puts "and1 is_memory: [get_property $and_inst is_memory]"
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puts "PASS: and instance properties"
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puts "--- Instance properties for register ---"
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set reg_inst [get_cells reg1]
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puts "reg1 is_buffer: [get_property $reg_inst is_buffer]"
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puts "reg1 is_inverter: [get_property $reg_inst is_inverter]"
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puts "reg1 is_clock_gate: [get_property $reg_inst is_clock_gate]"
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puts "reg1 is_macro: [get_property $reg_inst is_macro]"
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puts "reg1 is_memory: [get_property $reg_inst is_memory]"
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puts "PASS: reg instance properties"
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############################################################
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# LibertyCell properties: is_inverter, is_memory, dont_use, area
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############################################################
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puts "--- LibertyCell properties ---"
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set inv_cell [get_lib_cells NangateOpenCellLibrary/INV_X1]
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puts "INV_X1 is_buffer: [get_property $inv_cell is_buffer]"
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puts "INV_X1 is_inverter: [get_property $inv_cell is_inverter]"
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puts "INV_X1 is_memory: [get_property $inv_cell is_memory]"
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puts "INV_X1 dont_use: [get_property $inv_cell dont_use]"
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puts "INV_X1 area: [get_property $inv_cell area]"
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puts "PASS: INV_X1 liberty cell properties"
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set buf_cell [get_lib_cells NangateOpenCellLibrary/BUF_X1]
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puts "BUF_X1 is_buffer: [get_property $buf_cell is_buffer]"
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puts "BUF_X1 is_inverter: [get_property $buf_cell is_inverter]"
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puts "BUF_X1 is_memory: [get_property $buf_cell is_memory]"
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puts "BUF_X1 dont_use: [get_property $buf_cell dont_use]"
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puts "BUF_X1 area: [get_property $buf_cell area]"
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puts "PASS: BUF_X1 liberty cell properties"
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set dff_cell [get_lib_cells NangateOpenCellLibrary/DFF_X1]
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puts "DFF_X1 is_buffer: [get_property $dff_cell is_buffer]"
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puts "DFF_X1 is_inverter: [get_property $dff_cell is_inverter]"
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puts "DFF_X1 is_memory: [get_property $dff_cell is_memory]"
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puts "DFF_X1 dont_use: [get_property $dff_cell dont_use]"
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puts "DFF_X1 area: [get_property $dff_cell area]"
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puts "DFF_X1 filename: [get_property $dff_cell filename]"
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set dff_lib [get_property $dff_cell library]
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puts "DFF_X1 library: [get_name $dff_lib]"
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puts "PASS: DFF_X1 liberty cell properties"
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############################################################
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# Cell properties: full_name, library, filename
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############################################################
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puts "--- Cell properties ---"
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set cell_ref [get_property [get_cells buf1] cell]
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puts "cell name: [get_property $cell_ref name]"
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puts "cell full_name: [get_property $cell_ref full_name]"
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set cell_lib [get_property $cell_ref library]
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puts "cell library: [get_name $cell_lib]"
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puts "cell filename: [get_property $cell_ref filename]"
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puts "PASS: cell properties"
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############################################################
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# LibertyLibrary properties: filename
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############################################################
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puts "--- LibertyLibrary filename ---"
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set llib [get_libs NangateOpenCellLibrary]
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puts "lib name: [get_property $llib name]"
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puts "lib full_name: [get_property $llib full_name]"
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puts "lib filename: [get_property $llib filename]"
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puts "PASS: liberty library properties"
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############################################################
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# Pin properties: is_port, direction, pin_direction, is_hierarchical
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############################################################
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puts "--- Pin is_port, direction ---"
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set buf_a_pin [get_pins buf1/A]
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puts "buf1/A is_port: [get_property $buf_a_pin is_port]"
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puts "buf1/A direction: [get_property $buf_a_pin direction]"
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puts "buf1/A pin_direction: [get_property $buf_a_pin pin_direction]"
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puts "buf1/A is_hierarchical: [get_property $buf_a_pin is_hierarchical]"
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puts "buf1/A full_name: [get_property $buf_a_pin full_name]"
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puts "buf1/A name: [get_property $buf_a_pin name]"
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puts "buf1/A lib_pin_name: [get_property $buf_a_pin lib_pin_name]"
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set buf_z_pin [get_pins buf1/Z]
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puts "buf1/Z is_port: [get_property $buf_z_pin is_port]"
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puts "buf1/Z direction: [get_property $buf_z_pin direction]"
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puts "buf1/Z pin_direction: [get_property $buf_z_pin pin_direction]"
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puts "PASS: pin direction properties"
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puts "--- Pin is_clock, is_register_clock ---"
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set ck_pin [get_pins reg1/CK]
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puts "reg1/CK is_clock: [get_property $ck_pin is_clock]"
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puts "reg1/CK is_register_clock: [get_property $ck_pin is_register_clock]"
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set d_pin [get_pins reg1/D]
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puts "reg1/D is_clock: [get_property $d_pin is_clock]"
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puts "reg1/D is_register_clock: [get_property $d_pin is_register_clock]"
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puts "PASS: pin clock properties"
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puts "--- Pin activity ---"
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set p_activity [get_property [get_pins buf1/A] activity]
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puts "buf1/A activity: $p_activity"
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puts "PASS: pin activity"
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############################################################
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# Port properties: liberty_port, activity, slack/slew variants
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############################################################
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puts "--- Port liberty_port ---"
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set in_port [get_ports in1]
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set lport [get_property $in_port liberty_port]
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puts "in1 liberty_port: $lport"
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puts "PASS: port liberty_port"
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puts "--- Port activity ---"
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set p_act [get_property $in_port activity]
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puts "in1 activity: $p_act"
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puts "PASS: port activity"
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puts "--- Port slack variants ---"
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set out_port [get_ports out1]
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puts "out1 slack_max: [get_property $out_port slack_max]"
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puts "out1 slack_max_rise: [get_property $out_port slack_max_rise]"
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puts "out1 slack_max_fall: [get_property $out_port slack_max_fall]"
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puts "out1 slack_min: [get_property $out_port slack_min]"
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puts "out1 slack_min_rise: [get_property $out_port slack_min_rise]"
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puts "out1 slack_min_fall: [get_property $out_port slack_min_fall]"
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puts "PASS: port slack variants"
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puts "--- Port slew variants ---"
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puts "in1 slew_max: [get_property $in_port slew_max]"
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puts "in1 slew_max_rise: [get_property $in_port slew_max_rise]"
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puts "in1 slew_max_fall: [get_property $in_port slew_max_fall]"
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puts "in1 slew_min: [get_property $in_port slew_min]"
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puts "in1 slew_min_rise: [get_property $in_port slew_min_rise]"
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puts "in1 slew_min_fall: [get_property $in_port slew_min_fall]"
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puts "PASS: port slew variants"
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############################################################
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# Clock property: is_propagated
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############################################################
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puts "--- Clock is_propagated ---"
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set myclk [get_clocks clk]
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puts "clk is_propagated: [get_property $myclk is_propagated]"
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puts "clk is_virtual: [get_property $myclk is_virtual]"
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puts "clk is_generated: [get_property $myclk is_generated]"
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puts "clk period: [get_property $myclk period]"
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puts "clk name: [get_property $myclk name]"
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puts "clk full_name: [get_property $myclk full_name]"
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set clk_srcs [get_property $myclk sources]
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puts "clk sources: [llength $clk_srcs]"
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puts "PASS: clock properties"
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puts "--- Propagated clock property ---"
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set_propagated_clock [get_clocks clk]
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report_checks -path_delay max > /dev/null
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puts "clk is_propagated (after set): [get_property [get_clocks clk] is_propagated]"
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unset_propagated_clock [get_clocks clk]
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puts "PASS: propagated clock"
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############################################################
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# PathEnd property: points
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############################################################
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puts "--- PathEnd points property ---"
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set paths [find_timing_paths -path_delay max -endpoint_path_count 3]
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foreach pe $paths {
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set points [get_property $pe points]
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puts "PathEnd points count: [llength $points]"
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foreach pt $points {
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puts " point pin: [get_full_name [get_property $pt pin]]"
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puts " point arrival: [get_property $pt arrival]"
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}
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break
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}
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puts "PASS: PathEnd points"
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############################################################
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# Edge properties - is_disabled_cond checking
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############################################################
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puts "--- Edge disabled properties ---"
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set edges2 [get_timing_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]]
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foreach edge $edges2 {
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puts "edge sense: [get_property $edge sense]"
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puts "edge from_pin: [get_full_name [get_property $edge from_pin]]"
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puts "edge to_pin: [get_full_name [get_property $edge to_pin]]"
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puts "edge delay_min_rise: [get_property $edge delay_min_rise]"
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puts "edge delay_max_rise: [get_property $edge delay_max_rise]"
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puts "edge delay_min_fall: [get_property $edge delay_min_fall]"
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puts "edge delay_max_fall: [get_property $edge delay_max_fall]"
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break
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}
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puts "PASS: edge disabled properties"
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############################################################
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# LibertyPort properties: drive_resistance variants,
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# intrinsic_delay variants, capacitance, is_clock, is_register_clock
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############################################################
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puts "--- LibertyPort drive_resistance/intrinsic_delay ---"
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set lp_z [get_lib_pins NangateOpenCellLibrary/BUF_X1/Z]
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puts "BUF_X1/Z drive_resistance: [get_property $lp_z drive_resistance]"
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puts "BUF_X1/Z drive_resistance_min_rise: [get_property $lp_z drive_resistance_min_rise]"
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puts "BUF_X1/Z drive_resistance_max_rise: [get_property $lp_z drive_resistance_max_rise]"
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puts "BUF_X1/Z drive_resistance_min_fall: [get_property $lp_z drive_resistance_min_fall]"
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puts "BUF_X1/Z drive_resistance_max_fall: [get_property $lp_z drive_resistance_max_fall]"
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puts "BUF_X1/Z intrinsic_delay: [get_property $lp_z intrinsic_delay]"
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puts "BUF_X1/Z intrinsic_delay_min_rise: [get_property $lp_z intrinsic_delay_min_rise]"
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puts "BUF_X1/Z intrinsic_delay_max_rise: [get_property $lp_z intrinsic_delay_max_rise]"
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puts "BUF_X1/Z intrinsic_delay_min_fall: [get_property $lp_z intrinsic_delay_min_fall]"
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puts "BUF_X1/Z intrinsic_delay_max_fall: [get_property $lp_z intrinsic_delay_max_fall]"
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puts "BUF_X1/Z capacitance: [get_property $lp_z capacitance]"
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puts "BUF_X1/Z is_clock: [get_property $lp_z is_clock]"
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puts "BUF_X1/Z is_register_clock: [get_property $lp_z is_register_clock]"
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puts "BUF_X1/Z direction: [get_property $lp_z direction]"
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puts "BUF_X1/Z port_direction: [get_property $lp_z port_direction]"
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set lp_cell [get_property $lp_z lib_cell]
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puts "BUF_X1/Z lib_cell: [get_name $lp_cell]"
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puts "PASS: liberty port properties"
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puts "--- LibertyPort for clock pin ---"
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set lp_ck [get_lib_pins NangateOpenCellLibrary/DFF_X1/CK]
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puts "DFF_X1/CK is_clock: [get_property $lp_ck is_clock]"
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puts "DFF_X1/CK is_register_clock: [get_property $lp_ck is_register_clock]"
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puts "DFF_X1/CK direction: [get_property $lp_ck direction]"
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puts "PASS: DFF CK liberty port"
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set lp_d [get_lib_pins NangateOpenCellLibrary/DFF_X1/D]
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puts "DFF_X1/D is_clock: [get_property $lp_d is_clock]"
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puts "DFF_X1/D is_register_clock: [get_property $lp_d is_register_clock]"
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puts "PASS: DFF D liberty port"
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puts "ALL PASSED"
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