159 lines
4.2 KiB
Plaintext
159 lines
4.2 KiB
Plaintext
--- Instance is_buffer/is_inverter ---
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buf1 is_buffer: 1
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buf1 is_inverter: 0
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buf1 is_clock_gate: 0
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buf1 is_macro: 0
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buf1 is_memory: 0
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buf1 is_hierarchical: 0
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buf1 liberty_cell: BUF_X1
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buf1 cell: BUF_X1
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PASS: instance properties
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--- Instance properties for and gate ---
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and1 is_buffer: 0
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and1 is_inverter: 0
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and1 is_clock_gate: 0
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and1 is_macro: 0
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and1 is_memory: 0
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PASS: and instance properties
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--- Instance properties for register ---
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reg1 is_buffer: 0
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reg1 is_inverter: 0
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reg1 is_clock_gate: 0
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reg1 is_macro: 0
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reg1 is_memory: 0
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PASS: reg instance properties
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--- LibertyCell properties ---
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INV_X1 is_buffer: 0
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INV_X1 is_inverter: 1
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INV_X1 is_memory: 0
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INV_X1 dont_use: 0
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INV_X1 area: 0.532000
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PASS: INV_X1 liberty cell properties
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BUF_X1 is_buffer: 1
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BUF_X1 is_inverter: 0
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BUF_X1 is_memory: 0
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BUF_X1 dont_use: 0
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BUF_X1 area: 0.798000
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PASS: BUF_X1 liberty cell properties
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DFF_X1 is_buffer: 0
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DFF_X1 is_inverter: 0
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DFF_X1 is_memory: 0
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DFF_X1 dont_use: 0
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DFF_X1 area: 4.522000
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DFF_X1 filename: ../../test/nangate45/Nangate45_typ.lib
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DFF_X1 library: NangateOpenCellLibrary
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PASS: DFF_X1 liberty cell properties
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--- Cell properties ---
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cell name: BUF_X1
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cell full_name: NangateOpenCellLibrary/BUF_X1
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cell library: NangateOpenCellLibrary
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cell filename: ../../test/nangate45/Nangate45_typ.lib
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PASS: cell properties
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--- LibertyLibrary filename ---
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lib name: NangateOpenCellLibrary
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lib full_name: NangateOpenCellLibrary
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lib filename: ../../test/nangate45/Nangate45_typ.lib
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PASS: liberty library properties
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--- Pin is_port, direction ---
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buf1/A is_port: 0
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buf1/A direction: input
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buf1/A pin_direction: input
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buf1/A is_hierarchical: 0
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buf1/A full_name: buf1/A
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buf1/A name: A
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buf1/A lib_pin_name: A
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buf1/Z is_port: 0
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buf1/Z direction: output
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buf1/Z pin_direction: output
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PASS: pin direction properties
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--- Pin is_clock, is_register_clock ---
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reg1/CK is_clock: 1
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reg1/CK is_register_clock: 1
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reg1/D is_clock: 0
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reg1/D is_register_clock: 0
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PASS: pin clock properties
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--- Pin activity ---
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buf1/A activity: 1.00000e+07 0.250 propagated
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PASS: pin activity
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--- Port liberty_port ---
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in1 liberty_port: NULL
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PASS: port liberty_port
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--- Port activity ---
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in1 activity: 1.00000e+07 0.500 input
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PASS: port activity
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--- Port slack variants ---
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out1 slack_max: 7.899714
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out1 slack_max_rise: 7.899714
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out1 slack_max_fall: 7.901434
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out1 slack_min: 2.098566
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out1 slack_min_rise: 2.100286
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out1 slack_min_fall: 2.098566
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PASS: port slack variants
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--- Port slew variants ---
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in1 slew_max: 0.000000
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in1 slew_max_rise: 0.000000
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in1 slew_max_fall: 0.000000
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in1 slew_min: 0.000000
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in1 slew_min_rise: 0.000000
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in1 slew_min_fall: 0.000000
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PASS: port slew variants
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--- Clock is_propagated ---
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clk is_propagated: 0
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clk is_virtual: 0
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clk is_generated: 0
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clk period: 10.000000
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clk name: clk
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clk full_name: clk
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clk sources: 1
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PASS: clock properties
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--- Propagated clock property ---
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clk is_propagated (after set): 1
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PASS: propagated clock
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--- PathEnd points property ---
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PathEnd points count: 4
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point pin: reg1/Q
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point arrival: 0.083707
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point pin: buf2/A
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point arrival: 0.083707
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point pin: buf2/Z
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point arrival: 0.100286
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point pin: out1
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point arrival: 0.100286
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PASS: PathEnd points
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--- Edge disabled properties ---
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edge sense: positive_unate
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edge from_pin: buf1/A
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edge to_pin: buf1/Z
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edge delay_min_rise: 0.019582
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edge delay_max_rise: 0.019583
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edge delay_min_fall: 0.023405
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edge delay_max_fall: 0.023517
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PASS: edge disabled properties
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--- LibertyPort drive_resistance/intrinsic_delay ---
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BUF_X1/Z drive_resistance: 2.327937
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BUF_X1/Z drive_resistance_min_rise: 2.327937
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BUF_X1/Z drive_resistance_max_rise: 2.327937
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BUF_X1/Z drive_resistance_min_fall: 1.083897
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BUF_X1/Z drive_resistance_max_fall: 1.083897
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BUF_X1/Z intrinsic_delay: 0.018876
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BUF_X1/Z intrinsic_delay_min_rise: 0.013565
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BUF_X1/Z intrinsic_delay_max_rise: 0.013565
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BUF_X1/Z intrinsic_delay_min_fall: 0.018876
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BUF_X1/Z intrinsic_delay_max_fall: 0.018876
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BUF_X1/Z capacitance: 0.000000
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BUF_X1/Z is_clock: 0
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BUF_X1/Z is_register_clock: 0
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BUF_X1/Z direction: output
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BUF_X1/Z port_direction: output
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BUF_X1/Z lib_cell: BUF_X1
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PASS: liberty port properties
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--- LibertyPort for clock pin ---
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DFF_X1/CK is_clock: 1
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DFF_X1/CK is_register_clock: 1
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DFF_X1/CK direction: input
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PASS: DFF CK liberty port
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DFF_X1/D is_clock: 0
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DFF_X1/D is_register_clock: 0
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PASS: DFF D liberty port
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ALL PASSED
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