652 lines
21 KiB
Plaintext
652 lines
21 KiB
Plaintext
--- slow_drivers ---
|
|
slow drivers count: 3
|
|
reg1
|
|
and1
|
|
buf1
|
|
PASS: slow_drivers
|
|
--- set_load (port ext pin cap) ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: port ext pin cap
|
|
--- set_load -wire_load ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: port ext wire cap
|
|
--- set_fanout_load ---
|
|
Warning: search_network_sta_deep.tcl line 1, set_fanout_load not supported.
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: port ext fanout
|
|
--- set_input_transition ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: input_transition
|
|
--- set_drive ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: set_drive
|
|
--- set_driving_cell ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: driving_cell
|
|
--- set_wire_load_mode ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: wire_load_mode
|
|
--- report_tags ---
|
|
0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
|
1 v min/0 clk v (clock ideal) clk_src clk crpr_pin null
|
|
2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
|
3 v max/1 clk v (clock ideal) clk_src clk crpr_pin null
|
|
4 ^ min/0 clk ^ clk_src clk crpr_pin null input in1
|
|
5 v min/0 clk ^ clk_src clk crpr_pin null input in1
|
|
6 ^ max/1 clk ^ clk_src clk crpr_pin null input in1
|
|
7 v max/1 clk ^ clk_src clk crpr_pin null input in1
|
|
8 ^ min/0 clk ^ clk_src clk crpr_pin null input in2
|
|
9 v min/0 clk ^ clk_src clk crpr_pin null input in2
|
|
10 ^ max/1 clk ^ clk_src clk crpr_pin null input in2
|
|
11 v max/1 clk ^ clk_src clk crpr_pin null input in2
|
|
12 ^ min/0 clk ^ clk_src clk crpr_pin null
|
|
13 ^ max/1 clk ^ clk_src clk crpr_pin null
|
|
14 v min/0 clk ^ clk_src clk crpr_pin null
|
|
15 v max/1 clk ^ clk_src clk crpr_pin null
|
|
Longest hash bucket length 1 hash=15
|
|
PASS: report_tags
|
|
--- report_clk_infos ---
|
|
min/0 clk ^ clk_src clk
|
|
max/1 clk ^ clk_src clk
|
|
min/0 clk v clk_src clk
|
|
max/1 clk v clk_src clk
|
|
4 clk infos
|
|
PASS: report_clk_infos
|
|
--- report_tag_groups ---
|
|
Group 0 hash = 17966705655932391860 ( 134)
|
|
0 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
|
1 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
|
2 1 v min/0 clk v (clock ideal) clk_src clk crpr_pin null
|
|
3 3 v max/1 clk v (clock ideal) clk_src clk crpr_pin null
|
|
|
|
Group 1 hash = 2705662179234464818 ( 101)
|
|
0 4 ^ min/0 clk ^ clk_src clk crpr_pin null input in1
|
|
1 6 ^ max/1 clk ^ clk_src clk crpr_pin null input in1
|
|
2 5 v min/0 clk ^ clk_src clk crpr_pin null input in1
|
|
3 7 v max/1 clk ^ clk_src clk crpr_pin null input in1
|
|
|
|
Group 2 hash = 17969741592058791410 ( 82)
|
|
0 12 ^ min/0 clk ^ clk_src clk crpr_pin null
|
|
1 13 ^ max/1 clk ^ clk_src clk crpr_pin null
|
|
2 14 v min/0 clk ^ clk_src clk crpr_pin null
|
|
3 15 v max/1 clk ^ clk_src clk crpr_pin null
|
|
|
|
Longest hash bucket length 1 hash=82
|
|
PASS: report_tag_groups
|
|
--- report_path_count_histogram ---
|
|
4 15
|
|
PASS: report_path_count_histogram
|
|
--- tag/group/path counts ---
|
|
tags: 16
|
|
tag_groups: 3
|
|
clk_infos: 4
|
|
paths: 60
|
|
PASS: counts
|
|
--- report_tag_arrivals ---
|
|
Vertex out1
|
|
Group 2
|
|
^ min 0.100 / -2.000 12 clk ^ clk_src clk crpr_pin null prev buf2/Z ^ min/0 12 buf2/Z ^ -> out1 ^
|
|
v min 0.099 / -2.000 14 clk ^ clk_src clk crpr_pin null prev buf2/Z v min/0 14 buf2/Z v -> out1 v
|
|
^ max 0.100 / 8.000 13 clk ^ clk_src clk crpr_pin null prev buf2/Z ^ max/1 13 buf2/Z ^ -> out1 ^
|
|
v max 0.099 / 8.000 15 clk ^ clk_src clk crpr_pin null prev buf2/Z v max/1 15 buf2/Z v -> out1 v
|
|
Vertex out1
|
|
^ min 0.100 / -2.000 clk ^ clk_src clk crpr_pin null prev buf2/Z ^ min/0 12 buf2/Z ^ -> out1 ^
|
|
v min 0.099 / -2.000 clk ^ clk_src clk crpr_pin null prev buf2/Z v min/0 14 buf2/Z v -> out1 v
|
|
^ max 0.100 / 8.000 clk ^ clk_src clk crpr_pin null prev buf2/Z ^ max/1 13 buf2/Z ^ -> out1 ^
|
|
v max 0.099 / 8.000 clk ^ clk_src clk crpr_pin null prev buf2/Z v max/1 15 buf2/Z v -> out1 v
|
|
PASS: report_tag_arrivals
|
|
--- report_arrival_entries ---
|
|
PASS: report_arrival_entries
|
|
--- report_required_entries ---
|
|
Level 40
|
|
buf1/Z
|
|
buf2/Z
|
|
Level 10
|
|
reg1/CK
|
|
PASS: report_required_entries
|
|
--- find_requireds ---
|
|
PASS: find_requireds
|
|
--- report_annotated_delay ---
|
|
Not
|
|
Delay type Total Annotated Annotated
|
|
----------------------------------------------------------------
|
|
cell arcs 6 0 6
|
|
internal net arcs 3 0 3
|
|
net arcs from primary inputs 3 0 3
|
|
net arcs to primary outputs 1 0 1
|
|
----------------------------------------------------------------
|
|
13 0 13
|
|
PASS: report_annotated_delay
|
|
--- report_annotated_check ---
|
|
Not
|
|
Check type Total Annotated Annotated
|
|
----------------------------------------------------------------
|
|
cell setup arcs 1 0 1
|
|
cell hold arcs 1 0 1
|
|
cell width arcs 1 0 1
|
|
----------------------------------------------------------------
|
|
3 0 3
|
|
PASS: report_annotated_check
|
|
--- report_disabled_edges ---
|
|
PASS: report_disabled_edges
|
|
--- network editing ---
|
|
new_net: new_net
|
|
PASS: make_net
|
|
--- make_instance ---
|
|
new_inst: new_buf
|
|
PASS: make_instance
|
|
--- connect_pin ---
|
|
PASS: connect_pin A
|
|
PASS: connect_pin Z
|
|
--- disconnect_pin ---
|
|
PASS: disconnect_pin
|
|
--- disconnect_pin A ---
|
|
PASS: disconnect_pin A
|
|
--- delete_instance ---
|
|
PASS: delete_instance
|
|
--- delete_net ---
|
|
PASS: delete_net
|
|
--- replace_cell ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: replace_cell
|
|
--- replace_cell back ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: replace_cell back
|
|
--- write_verilog ---
|
|
PASS: write_verilog
|
|
--- write_sdc ---
|
|
PASS: write_sdc
|
|
--- vertex queries ---
|
|
worst_arrival pin: out1
|
|
worst_arrival arrival: 1.0032709385487948e-10
|
|
worst_slack pin: out1
|
|
worst_slack slack: 7.899672915812062e-9
|
|
PASS: vertex queries
|
|
--- report_path_end header/footer ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 v reg1/Q (DFF_X1)
|
|
0.02 0.10 v buf2/Z (BUF_X1)
|
|
0.00 0.10 v out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.02 1.03 v and1/ZN (AND2_X1)
|
|
0.02 1.05 v buf1/Z (BUF_X1)
|
|
0.00 1.05 v reg1/D (DFF_X1)
|
|
1.05 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
8.91 slack (MET)
|
|
|
|
|
|
PASS: report_path_end header/footer
|
|
--- json format ---
|
|
{"checks": [
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "out1",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 1.500e-17,
|
|
"slew": 3.668e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.668e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.003e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 8.000e-09,
|
|
"slack": 7.900e-09
|
|
}
|
|
]
|
|
}
|
|
PASS: json format
|
|
--- set_report_path_field_properties ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Total Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: field properties
|
|
--- report_checks -path_delay min_max ---
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Total Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ in2 (in)
|
|
0.03 1.03 ^ and1/ZN (AND2_X1)
|
|
0.02 1.05 ^ buf1/Z (BUF_X1)
|
|
0.00 1.05 ^ reg1/D (DFF_X1)
|
|
1.05 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-1.05 data arrival time
|
|
---------------------------------------------------------
|
|
1.04 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Total Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
PASS: min_max
|
|
ALL PASSED
|