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OpenSTA/search/test/search_multicorner_analysis.ok

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--- set_analysis_type bc_wc ---
PASS: analysis_type bc_wc
--- set_analysis_type single ---
PASS: analysis_type single
--- set_analysis_type on_chip_variation ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.08 data arrival time
---------------------------------------------------------
7.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 v reg1/Q (DFF_X1)
0.03 0.11 v buf3/Z (BUF_X1)
0.00 0.11 v reg2/D (DFF_X1)
0.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-0.11 data arrival time
---------------------------------------------------------
0.11 slack (MET)
PASS: analysis_type on_chip_variation
--- set_voltage ---
PASS: set_voltage
--- set_voltage on net ---
PASS: set_voltage on net
--- set_load (port external pin cap) ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.08 data arrival time
---------------------------------------------------------
7.92 slack (MET)
PASS: set_load
--- set_load with -min/-max ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.08 data arrival time
---------------------------------------------------------
7.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 v reg1/Q (DFF_X1)
0.03 0.11 v buf3/Z (BUF_X1)
0.00 0.11 v reg2/D (DFF_X1)
0.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-0.11 data arrival time
---------------------------------------------------------
0.11 slack (MET)
PASS: set_load min/max
--- set_load -wire_load ---
PASS: set_load wire
--- set_fanout_load ---
Warning: search_multicorner_analysis.tcl line 1, set_fanout_load not supported.
PASS: set_fanout_load
--- Net capacitance ---
Net n1 capacitance: 9.46813957836449e-16
Net n1 pin_cap: 9.46813957836449e-16
Net n1 wire_cap: 0.0
PASS: net capacitance
--- set_wire_load_mode ---
PASS: set_wire_load_mode
--- report_checks with various fields after load changes ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
1 0.09 0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
0.01 0.00 0.08 ^ out1 (out)
0.08 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
-----------------------------------------------------------------------------
8.00 data required time
-0.08 data arrival time
-----------------------------------------------------------------------------
7.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
2 3.88 0.01 0.08 0.08 v reg1/Q (DFF_X1)
1 1.06 0.01 0.03 0.11 v buf3/Z (BUF_X1)
0.01 0.00 0.11 v reg2/D (DFF_X1)
0.11 data arrival time
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
-----------------------------------------------------------------------------
0.00 data required time
-0.11 data arrival time
-----------------------------------------------------------------------------
0.11 slack (MET)
PASS: report_checks fields after load
--- set_input_transition ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Slew Delay Time Description
----------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
0.01 0.00 0.08 ^ out1 (out)
0.08 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
----------------------------------------------------------------
8.00 data required time
-0.08 data arrival time
----------------------------------------------------------------
7.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Slew Delay Time Description
----------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
0.01 0.08 0.08 v reg1/Q (DFF_X1)
0.01 0.03 0.11 v buf3/Z (BUF_X1)
0.01 0.00 0.11 v reg2/D (DFF_X1)
0.11 data arrival time
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
----------------------------------------------------------------
0.00 data required time
-0.11 data arrival time
----------------------------------------------------------------
0.11 slack (MET)
PASS: set_input_transition
--- set_drive on port ---
PASS: set_drive
--- set_driving_cell ---
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v in1 (in)
0.02 1.03 v and1/ZN (AND2_X1)
0.04 1.07 v or1/ZN (OR2_X1)
0.03 1.10 v buf1/Z (BUF_X1)
0.01 1.11 ^ inv1/ZN (INV_X1)
0.02 1.13 ^ buf2/Z (BUF_X2)
0.00 1.13 ^ reg1/D (DFF_X1)
1.13 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-1.13 data arrival time
---------------------------------------------------------
8.84 slack (MET)
PASS: set_driving_cell
--- Timing derate with cell-level ---
PASS: timing derate cell/net
--- report_checks after all modifications ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.08 data arrival time
---------------------------------------------------------
7.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 v reg1/Q (DFF_X1)
0.03 0.11 v buf3/Z (BUF_X1)
0.00 0.11 v reg2/D (DFF_X1)
0.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-0.11 data arrival time
---------------------------------------------------------
0.11 slack (MET)
{"checks": [
{
"type": "output_delay",
"path_group": "clk",
"path_type": "max",
"startpoint": "reg2/Q",
"endpoint": "out1",
"source_clock": "clk",
"source_clock_edge": "rise",
"source_clock_path": [
{
"instance": "",
"cell": "search_multicorner_analysis",
"verilog_src": "",
"pin": "clk",
"arrival": 0.000e+00,
"capacitance": 7.798e-16,
"slew": 0.000e+00
},
{
"instance": "ckbuf",
"cell": "CLKBUF_X1",
"verilog_src": "",
"pin": "ckbuf/A",
"net": "clk",
"arrival": 0.000e+00,
"slew": 0.000e+00
},
{
"instance": "ckbuf",
"cell": "CLKBUF_X1",
"verilog_src": "",
"pin": "ckbuf/Z",
"net": "clk_buf",
"arrival": 2.604e-11,
"capacitance": 1.899e-15,
"slew": 8.412e-12
},
{
"instance": "reg2",
"cell": "DFF_X1",
"verilog_src": "",
"pin": "reg2/CK",
"net": "clk_buf",
"arrival": 2.604e-11,
"slew": 8.412e-12
}
],
"source_path": [
{
"instance": "reg2",
"cell": "DFF_X1",
"verilog_src": "",
"pin": "reg2/Q",
"net": "out1",
"arrival": 8.169e-11,
"capacitance": 9.000e-17,
"slew": 5.746e-12
},
{
"instance": "",
"cell": "search_multicorner_analysis",
"verilog_src": "",
"pin": "out1",
"arrival": 8.169e-11,
"slew": 5.746e-12
}
],
"target_clock": "clk",
"target_clock_edge": "rise",
"data_arrival_time": 8.169e-11,
"crpr": 0.000e+00,
"margin": 2.000e-09,
"required_time": 8.000e-09,
"slack": 7.918e-09
}
]
}
PASS: final report
--- report_check_types verbose after modifications ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 v reg1/Q (DFF_X1)
0.03 0.11 v buf3/Z (BUF_X1)
0.00 0.11 v reg2/D (DFF_X1)
0.11 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg2/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-0.11 data arrival time
---------------------------------------------------------
0.11 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.08 data arrival time
---------------------------------------------------------
7.92 slack (MET)
max slew
Pin or1/ZN ^
max slew 0.20
slew 0.02
----------------
Slack 0.18 (MET)
max capacitance
Pin reg1/Q ^
max capacitance 60.73
capacitance 4.38
-----------------------
Slack 56.35 (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.03 0.03 clock network delay (ideal)
0.00 0.03 reg1/CK
0.03 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.03 5.03 clock network delay (ideal)
0.00 5.03 reg1/CK
0.00 5.03 clock reconvergence pessimism
5.03 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
PASS: check_types
--- write_sdc ---
PASS: write_sdc
--- set_resistance on net ---
PASS: set_resistance
--- set_max_area ---
PASS: set_max_area
--- isClock / isPropagatedClock queries ---
PASS: isClock queries
ALL PASSED
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