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OpenSTA/search/test/search_limit_violations.ok

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=== SLEW LIMIT CHECKS ===
--- set_max_transition tight limit ---
max slew
Pin reg1/QN v
max slew 0.00
slew 0.01
----------------
Slack -0.01 (VIOLATED)
PASS: tight slew limit verbose
--- report_check_types -max_slew only ---
max slew
Pin Limit Slew Slack
------------------------------------------------------------
reg1/QN 0.00 0.01 -0.01 (VIOLATED)
PASS: slew limit short
--- report_check_types -max_slew -violators ---
max slew
Pin Limit Slew Slack
------------------------------------------------------------
reg1/QN 0.00 0.01 -0.01 (VIOLATED)
reg2/QN 0.00 0.01 -0.01 (VIOLATED)
reg3/QN 0.00 0.01 -0.01 (VIOLATED)
buf3/A 0.00 0.01 -0.01 (VIOLATED)
buf4/A 0.00 0.01 -0.01 (VIOLATED)
buf5/A 0.00 0.01 -0.01 (VIOLATED)
inv2/ZN 0.00 0.01 -0.01 (VIOLATED)
and2/A2 0.00 0.01 -0.01 (VIOLATED)
or1/ZN 0.00 0.01 -0.01 (VIOLATED)
buf6/A 0.00 0.01 -0.01 (VIOLATED)
reg1/Q 0.00 0.01 -0.01 (VIOLATED)
buf1/Z 0.00 0.01 -0.01 (VIOLATED)
inv1/A 0.00 0.01 -0.01 (VIOLATED)
buf2/Z 0.00 0.01 -0.01 (VIOLATED)
inv2/A 0.00 0.01 -0.01 (VIOLATED)
and2/ZN 0.00 0.01 -0.01 (VIOLATED)
buf1/A 0.00 0.01 -0.01 (VIOLATED)
and1/ZN 0.00 0.01 -0.01 (VIOLATED)
and2/A1 0.00 0.01 -0.01 (VIOLATED)
buf3/Z 0.00 0.01 -0.00 (VIOLATED)
buf4/Z 0.00 0.01 -0.00 (VIOLATED)
buf5/Z 0.00 0.01 -0.00 (VIOLATED)
reg1/D 0.00 0.01 -0.00 (VIOLATED)
reg2/D 0.00 0.01 -0.00 (VIOLATED)
reg3/D 0.00 0.01 -0.00 (VIOLATED)
out2 0.00 0.01 -0.00 (VIOLATED)
out3 0.00 0.01 -0.00 (VIOLATED)
reg2/Q 0.00 0.01 -0.00 (VIOLATED)
reg3/Q 0.00 0.01 -0.00 (VIOLATED)
buf2/A 0.00 0.00 -0.00 (VIOLATED)
inv1/ZN 0.00 0.00 -0.00 (VIOLATED)
out1 0.00 0.00 -0.00 (VIOLATED)
buf6/Z 0.00 0.00 -0.00 (VIOLATED)
PASS: slew violators
--- set_max_transition on clock ---
max slew
Pin reg1/QN v
max slew 0.00
slew 0.01
----------------
Slack -0.01 (VIOLATED)
PASS: clock slew limit
--- set_max_transition on port ---
max slew
Pin reg1/QN v
max slew 0.00
slew 0.01
----------------
Slack -0.01 (VIOLATED)
PASS: port slew limit
=== CAPACITANCE LIMIT CHECKS ===
--- set_max_capacitance tight limit ---
max capacitance
Pin inv2/ZN ^
max capacitance 0.00
capacitance 2.92
-----------------------
Slack -2.92 (VIOLATED)
PASS: tight cap limit verbose
--- report_check_types -max_capacitance only ---
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
inv2/ZN 0.00 2.92 -2.92 (VIOLATED)
PASS: cap limit short
--- report_check_types -max_capacitance -violators ---
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
inv2/ZN 0.00 2.92 -2.92 (VIOLATED)
buf1/Z 0.00 1.70 -1.70 (VIOLATED)
buf2/Z 0.00 1.70 -1.70 (VIOLATED)
buf3/Z 0.00 1.14 -1.14 (VIOLATED)
buf4/Z 0.00 1.14 -1.14 (VIOLATED)
buf5/Z 0.00 1.14 -1.14 (VIOLATED)
and2/ZN 0.00 0.97 -0.97 (VIOLATED)
inv1/ZN 0.00 0.97 -0.97 (VIOLATED)
reg1/Q 0.00 0.97 -0.97 (VIOLATED)
in2 0.00 0.97 -0.97 (VIOLATED)
or1/ZN 0.00 0.97 -0.97 (VIOLATED)
in3 0.00 0.95 -0.95 (VIOLATED)
in4 0.00 0.94 -0.94 (VIOLATED)
in1 0.00 0.92 -0.92 (VIOLATED)
and1/ZN 0.00 0.92 -0.92 (VIOLATED)
PASS: cap violators
--- set_max_capacitance on port ---
max capacitance
Pin inv2/ZN ^
max capacitance 0.00
capacitance 2.92
-----------------------
Slack -2.92 (VIOLATED)
PASS: port cap limit
=== FANOUT LIMIT CHECKS ===
--- set_max_fanout tight limit ---
max fanout
Pin inv2/ZN
max fanout 1
fanout 3
-----------------
Slack -2 (VIOLATED)
PASS: tight fanout limit verbose
--- report_check_types -max_fanout only ---
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
inv2/ZN 1 3 -2 (VIOLATED)
PASS: fanout limit short
--- report_check_types -max_fanout -violators ---
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
inv2/ZN 1 3 -2 (VIOLATED)
PASS: fanout violators
--- set_max_fanout on port ---
max fanout
Pin inv2/ZN
max fanout 1
fanout 3
-----------------
Slack -2 (VIOLATED)
PASS: port fanout limit
=== PULSE WIDTH CHECKS ===
--- report_pulse_width_checks ---
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg1/CK (high) 0.05 5.00 4.95 (MET)
reg2/CK (high) 0.05 5.00 4.95 (MET)
reg3/CK (high) 0.05 5.00 4.95 (MET)
reg1/CK (low) 0.05 5.00 4.95 (MET)
reg2/CK (low) 0.05 5.00 4.95 (MET)
reg3/CK (low) 0.05 5.00 4.95 (MET)
PASS: pulse_width default
--- report_pulse_width_checks -verbose ---
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg1/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg2/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
Pin: reg3/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg3/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg3/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg1/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg2/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
Pin: reg3/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg3/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg3/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
PASS: pulse_width verbose
--- report_pulse_width_checks on specific pin ---
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg1/CK (high) 0.05 5.00 4.95 (MET)
reg1/CK (low) 0.05 5.00 4.95 (MET)
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg2/CK (high) 0.05 5.00 4.95 (MET)
reg2/CK (low) 0.05 5.00 4.95 (MET)
PASS: pulse_width specific pins
--- set_min_pulse_width ---
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg1/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg1/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg2/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg2/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg3/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg3/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg3/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg3/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg3/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg3/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
PASS: min_pulse_width on clock
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg1/CK (high) 4.00 5.00 1.00 (MET)
reg1/CK (low) 0.05 5.00 4.95 (MET)
PASS: min_pulse_width on pin
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg2/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg2/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg3/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg3/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg3/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg3/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg3/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg3/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg1/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
4.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
1.00 slack (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg1/CK
5.00 open edge arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 reg1/CK
0.00 10.00 clock reconvergence pessimism
10.00 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (low)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
PASS: min_pulse_width on instance
--- report_check_types -min_pulse_width ---
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg2/CK (high) 5.00 5.00 0.00 (MET)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg2/CK
0.00 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 reg2/CK
0.00 5.00 clock reconvergence pessimism
5.00 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
0.00 slack (MET)
PASS: check_types pulse_width
=== MIN PERIOD CHECKS ===
--- report_clock_min_period ---
clk period_min = 0.00 fmax = inf
PASS: min_period
--- report_clock_min_period -include_port_paths ---
clk period_min = 2.10 fmax = 476.13
PASS: min_period with port paths
--- report_clock_min_period -clocks ---
clk period_min = 0.00 fmax = inf
PASS: min_period specific clock
--- Tight clock period for min_period violations ---
PASS: min_period violations
--- report_clock_min_period with violation ---
clk period_min = 0.00 fmax = inf
PASS: clock_min_period with violation
=== MAX SKEW CHECKS ===
--- report_check_types -max_skew ---
PASS: max_skew
=== COMBINED CHECKS ===
--- report_check_types -violators (all) ---
Group Slack
--------------------------------------------
clk -2.09
clk -2.07
clk -2.07
clk -1.19
clk -1.19
clk -1.19
max slew
Pin Limit Slew Slack
------------------------------------------------------------
reg1/QN 0.00 0.01 -0.01 (VIOLATED)
reg2/QN 0.00 0.01 -0.01 (VIOLATED)
reg3/QN 0.00 0.01 -0.01 (VIOLATED)
buf3/A 0.00 0.01 -0.01 (VIOLATED)
buf4/A 0.00 0.01 -0.01 (VIOLATED)
buf5/A 0.00 0.01 -0.01 (VIOLATED)
inv2/ZN 0.00 0.01 -0.01 (VIOLATED)
and2/A2 0.00 0.01 -0.01 (VIOLATED)
or1/ZN 0.00 0.01 -0.01 (VIOLATED)
buf6/A 0.00 0.01 -0.01 (VIOLATED)
reg1/Q 0.00 0.01 -0.01 (VIOLATED)
buf1/Z 0.00 0.01 -0.01 (VIOLATED)
inv1/A 0.00 0.01 -0.01 (VIOLATED)
buf2/Z 0.00 0.01 -0.01 (VIOLATED)
inv2/A 0.00 0.01 -0.01 (VIOLATED)
and2/ZN 0.00 0.01 -0.01 (VIOLATED)
buf1/A 0.00 0.01 -0.01 (VIOLATED)
and1/ZN 0.00 0.01 -0.01 (VIOLATED)
and2/A1 0.00 0.01 -0.01 (VIOLATED)
buf3/Z 0.00 0.01 -0.00 (VIOLATED)
buf4/Z 0.00 0.01 -0.00 (VIOLATED)
buf5/Z 0.00 0.01 -0.00 (VIOLATED)
reg1/D 0.00 0.01 -0.00 (VIOLATED)
reg2/D 0.00 0.01 -0.00 (VIOLATED)
reg3/D 0.00 0.01 -0.00 (VIOLATED)
out2 0.00 0.01 -0.00 (VIOLATED)
out3 0.00 0.01 -0.00 (VIOLATED)
reg2/Q 0.00 0.01 -0.00 (VIOLATED)
reg3/Q 0.00 0.01 -0.00 (VIOLATED)
buf2/A 0.00 0.00 -0.00 (VIOLATED)
inv1/ZN 0.00 0.00 -0.00 (VIOLATED)
out1 0.00 0.00 -0.00 (VIOLATED)
buf6/Z 0.00 0.00 -0.00 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
inv2/ZN 1 3 -2 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
inv2/ZN 0.00 2.92 -2.92 (VIOLATED)
buf1/Z 0.00 1.70 -1.70 (VIOLATED)
buf2/Z 0.00 1.70 -1.70 (VIOLATED)
buf3/Z 0.00 1.14 -1.14 (VIOLATED)
buf4/Z 0.00 1.14 -1.14 (VIOLATED)
buf5/Z 0.00 1.14 -1.14 (VIOLATED)
and2/ZN 0.00 0.97 -0.97 (VIOLATED)
inv1/ZN 0.00 0.97 -0.97 (VIOLATED)
reg1/Q 0.00 0.97 -0.97 (VIOLATED)
in2 0.00 0.97 -0.97 (VIOLATED)
or1/ZN 0.00 0.97 -0.97 (VIOLATED)
in3 0.00 0.95 -0.95 (VIOLATED)
in4 0.00 0.94 -0.94 (VIOLATED)
in1 0.00 0.92 -0.92 (VIOLATED)
and1/ZN 0.00 0.92 -0.92 (VIOLATED)
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg2/CK (high) 5.00 0.01 -4.99 (VIOLATED)
reg2/CK (low) 5.00 0.01 -4.99 (VIOLATED)
reg3/CK (high) 5.00 0.01 -4.99 (VIOLATED)
reg3/CK (low) 5.00 0.01 -4.99 (VIOLATED)
reg1/CK (high) 4.00 0.01 -3.99 (VIOLATED)
reg1/CK (low) 0.05 0.01 -0.05 (VIOLATED)
PASS: all violators
--- report_check_types verbose (all) ---
Startpoint: in3 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in3 (in)
0.02 1.02 ^ or1/ZN (OR2_X1)
0.03 1.04 ^ and2/ZN (AND2_X1)
0.02 1.07 ^ buf1/Z (BUF_X1)
0.01 1.07 v inv1/ZN (INV_X1)
0.02 1.10 v buf2/Z (BUF_X1)
0.01 1.11 ^ inv2/ZN (INV_X1)
0.02 1.13 ^ buf3/Z (BUF_X1)
0.00 1.13 ^ reg1/D (DFF_X1)
1.13 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.13 data arrival time
---------------------------------------------------------
1.12 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf6/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
0.01 0.01 clock clk (rise edge)
0.00 0.01 clock network delay (ideal)
0.00 0.01 clock reconvergence pessimism
-2.00 -1.99 output external delay
-1.99 data required time
---------------------------------------------------------
-1.99 data required time
-0.10 data arrival time
---------------------------------------------------------
-2.09 slack (VIOLATED)
max slew
Pin reg1/QN v
max slew 0.00
slew 0.01
----------------
Slack -0.01 (VIOLATED)
max fanout
Pin inv2/ZN
max fanout 1
fanout 3
-----------------
Slack -2 (VIOLATED)
max capacitance
Pin inv2/ZN ^
max capacitance 0.00
capacitance 2.92
-----------------------
Slack -2.92 (VIOLATED)
Pin: reg2/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 reg2/CK
0.00 open edge arrival time
0.01 0.01 clock clk (fall edge)
0.00 0.01 clock network delay (ideal)
0.00 0.01 reg2/CK
0.00 0.01 clock reconvergence pessimism
0.01 close edge arrival time
---------------------------------------------------------
5.00 required pulse width (high)
0.01 actual pulse width
---------------------------------------------------------
-4.99 slack (VIOLATED)
PASS: all verbose
ALL PASSED
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