707 lines
23 KiB
Plaintext
707 lines
23 KiB
Plaintext
--- Latch timing max ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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PASS: latch max
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--- Latch timing min ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.05 0.05 ^ latch1/Q (DLH_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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PASS: latch min
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--- report_checks to latch output ---
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Startpoint: latch2 (positive level-sensitive latch clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.11 1.11 time given to startpoint
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0.00 1.11 v latch2/D (DLH_X1)
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0.06 1.16 v latch2/Q (DLH_X1)
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0.02 1.19 v buf2/Z (BUF_X1)
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0.00 1.19 v out1 (out)
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1.19 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-1.19 data arrival time
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---------------------------------------------------------
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6.81 slack (MET)
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Startpoint: latch2 (positive level-sensitive latch clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch2/G (DLH_X1)
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0.05 0.05 ^ latch2/Q (DLH_X1)
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0.02 0.07 ^ buf2/Z (BUF_X1)
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0.00 0.07 ^ out1 (out)
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0.07 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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-2.00 -2.00 output external delay
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-2.00 data required time
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---------------------------------------------------------
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-2.00 data required time
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-0.07 data arrival time
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---------------------------------------------------------
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2.07 slack (MET)
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PASS: latch output full_clock_expanded
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--- report_checks to reg output ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.02 0.10 v buf3/Z (BUF_X1)
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0.00 0.10 v out2 (out)
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0.10 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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-2.00 -2.00 output external delay
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-2.00 data required time
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---------------------------------------------------------
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-2.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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2.10 slack (MET)
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PASS: reg output full_clock_expanded
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--- report_checks format full_clock ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.05 0.05 ^ latch1/Q (DLH_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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PASS: full_clock format
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--- report_checks format short ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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PASS: short format
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--- report_checks format end ---
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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latch2/D (DLH_X1) 1.11 1.11 0.00 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.01 0.05 0.05 (MET)
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PASS: end format
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--- report_checks format summary ---
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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latch1/Q (DLH_X1) latch2/D (DLH_X1) 0.00
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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latch1/Q (DFF_X1) reg1/D (DFF_X1) 0.05
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PASS: summary format
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--- report_checks format json ---
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{"checks": [
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{
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"type": "latch_check",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "latch1/Q",
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"endpoint": "latch2/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_latch",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 2.921e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "latch1",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch1/G",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "latch1",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch1/Q",
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"net": "n3",
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"arrival": 1.106e-09,
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"capacitance": 1.932e-15,
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"slew": 1.074e-11
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},
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{
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"instance": "latch2",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch2/D",
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"net": "n3",
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"arrival": 1.106e-09,
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"slew": 1.074e-11
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "search_latch",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 2.921e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "latch2",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch2/G",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"data_arrival_time": 1.106e-09,
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"crpr": 0.000e+00,
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"margin": 5.497e-11,
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"required_time": 1.106e-09,
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"slack": 0.000e+00
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}
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]
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}
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{"checks": [
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{
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"type": "check",
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"path_group": "clk",
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"path_type": "min",
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"startpoint": "latch1/Q",
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"endpoint": "reg1/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_latch",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 2.921e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "latch1",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch1/G",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "latch1",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch1/Q",
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"net": "n3",
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"arrival": 5.291e-11,
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"capacitance": 2.054e-15,
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"slew": 9.761e-12
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/D",
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"net": "n3",
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"arrival": 5.291e-11,
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"slew": 9.761e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "search_latch",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 2.921e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"data_arrival_time": 5.291e-11,
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"crpr": -0.000e+00,
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"margin": 6.024e-12,
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"required_time": 6.024e-12,
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"slack": 4.688e-11
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}
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]
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}
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PASS: json format
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--- report_checks format slack_only ---
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Group Slack
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--------------------------------------------
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clk 0.00
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Group Slack
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--------------------------------------------
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clk 0.05
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PASS: slack_only format
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--- find_timing_paths latch check ---
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Found 18 max paths
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is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch1/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0
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is_latch_check: 1 is_check: 0 pin=latch2/D slack=0.0
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is_latch_check: 0 is_check: 0 pin=out1 slack=6.813221542500969e-9
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is_latch_check: 0 is_check: 0 pin=out1 slack=6.868384527791704e-9
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is_latch_check: 0 is_check: 0 pin=out2 slack=7.899713772019368e-9
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is_latch_check: 0 is_check: 0 pin=out2 slack=7.901434173618327e-9
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is_latch_check: 0 is_check: 0 pin=out1 slack=7.923797618047956e-9
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is_latch_check: 0 is_check: 0 pin=out1 slack=7.934120027641711e-9
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is_latch_check: 0 is_check: 1 pin=reg1/D slack=8.852826915983769e-9
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is_latch_check: 0 is_check: 1 pin=reg1/D slack=8.88718165725777e-9
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is_latch_check: 0 is_check: 1 pin=reg1/D slack=9.902577424725223e-9
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is_latch_check: 0 is_check: 1 pin=reg1/D slack=9.91532278504792e-9
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PASS: find_timing_paths latch
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--- find_timing_paths min latch ---
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Found 12 min paths
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is_latch_check: 0 is_check: 1 pin=reg1/D slack=4.688082214099332e-11
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is_latch_check: 0 is_check: 1 pin=reg1/D slack=5.435544375709256e-11
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is_latch_check: 0 is_check: 0 pin=out1 slack=2.065880133628184e-9
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is_latch_check: 0 is_check: 0 pin=out1 slack=2.076201877088124e-9
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is_latch_check: 0 is_check: 0 pin=out2 slack=2.0985655435623585e-9
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is_latch_check: 0 is_check: 0 pin=out2 slack=2.1002859451613176e-9
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is_latch_check: 0 is_check: 1 pin=latch2/D slack=5.041872697120198e-9
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is_latch_check: 0 is_check: 1 pin=latch2/D slack=5.044073603244215e-9
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is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.033108235214968e-9
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is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.034398758458792e-9
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is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.034420962919285e-9
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is_latch_check: 0 is_check: 1 pin=latch1/D slack=6.036642297146955e-9
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PASS: find_timing_paths min latch
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--- Latch path reports with fields ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 0.00 1.05 v latch1/D (DLH_X1)
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2 1.93 0.01 0.06 1.11 v latch1/Q (DLH_X1)
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n3 (net)
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0.01 0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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-----------------------------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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-----------------------------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ latch1/G (DLH_X1)
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2 2.05 0.01 0.05 0.05 ^ latch1/Q (DLH_X1)
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n3 (net)
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0.01 0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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-----------------------------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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-----------------------------------------------------------------------------
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0.05 slack (MET)
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PASS: latch fields
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--- set_latch_borrow_limit ---
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PASS: latch_borrow_limit pin
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PASS: latch_borrow_limit inst
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PASS: latch_borrow_limit clock
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--- report_clock_properties ---
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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PASS: clock_properties
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--- report_clock_skew ---
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Clock clk
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0.00 source latency latch1/G ^
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0.00 target latency latch2/G v
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0.00 CRPR
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--------------
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0.00 setup skew
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Clock clk
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0.00 source latency latch1/G ^
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0.00 target latency latch2/G v
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0.00 CRPR
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--------------
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0.00 hold skew
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PASS: clock_skew
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--- all_registers -level_sensitive ---
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Level-sensitive cells: 2
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latch1
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latch2
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Level-sensitive data pins: 2
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latch1/D
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latch2/D
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Level-sensitive clock pins: 2
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latch1/G
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latch2/G
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Level-sensitive output pins: 2
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latch1/Q
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latch2/Q
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PASS: all_registers level_sensitive
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--- all_registers -edge_triggered ---
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Edge-triggered cells: 1
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reg1
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PASS: all_registers edge_triggered
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--- pulse width checks ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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reg1/CK (low) 0.05 5.00 4.95 (MET)
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latch1/G (high) 0.04 5.00 4.96 (MET)
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latch2/G (high) 0.04 5.00 4.96 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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5.00 open edge arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 reg1/CK
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0.00 10.00 clock reconvergence pessimism
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10.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (low)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Pin: latch1/G
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 latch1/G
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 latch1/G
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.04 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.96 slack (MET)
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Pin: latch2/G
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 latch2/G
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 latch2/G
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.04 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.96 slack (MET)
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PASS: pulse_width_checks
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--- min period ---
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clk period_min = 1.15 fmax = 871.71
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clk period_min = 3.19 fmax = 313.80
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PASS: min_period
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ALL PASSED
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