268 lines
10 KiB
Tcl
268 lines
10 KiB
Tcl
# Test deeper Genclks.cc paths, latch timing (Latches.cc),
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# unconstrained path reporting, and PathEnd subclass coverage.
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# Targets: Genclks.cc srcFilter, updateGeneratedClks, srcPath,
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# GenclkInfo, GenclkSrcArrivalVisitor,
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# PathEnd.cc PathEndLatchCheck, PathEndGatedClock,
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# PathEndUnconstrained, PathEndOutputDelay,
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# ReportPath.cc reportShort/Full for latch, gated clock,
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# unconstrained, output delay path ends,
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# reportGenClkSrcAndPath, reportGenClkSrcPath1,
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# reportUnclockedEndpoint,
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# VisitPathEnds.cc clockGatingMargin,
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# Search.cc pathClkPathArrival
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_latch.v
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link_design search_latch
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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report_checks > /dev/null
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############################################################
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# Latch timing checks
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############################################################
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puts "--- report_checks max (latch paths) ---"
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report_checks -path_delay max
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puts "PASS: latch max"
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puts "--- report_checks min (latch paths) ---"
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report_checks -path_delay min
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puts "PASS: latch min"
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puts "--- report_checks -format full_clock ---"
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report_checks -path_delay max -format full_clock
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puts "PASS: latch full_clock"
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puts "--- report_checks -format full_clock_expanded ---"
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report_checks -path_delay max -format full_clock_expanded
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puts "PASS: latch full_clock_expanded"
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puts "--- report_checks -format short ---"
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report_checks -path_delay max -format short
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puts "PASS: latch short"
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puts "--- report_checks -format end ---"
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report_checks -path_delay max -format end
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puts "PASS: latch end"
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puts "--- report_checks -format summary ---"
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report_checks -path_delay max -format summary
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puts "PASS: latch summary"
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puts "--- report_checks -format slack_only ---"
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report_checks -path_delay max -format slack_only
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puts "PASS: latch slack_only"
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puts "--- report_checks -format json ---"
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report_checks -path_delay max -format json
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puts "PASS: latch json"
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############################################################
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# PathEnd type queries on latch paths
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############################################################
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puts "--- PathEnd queries on latch ---"
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set paths_latch [find_timing_paths -path_delay max -endpoint_path_count 10 -group_path_count 20]
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puts "Found [llength $paths_latch] paths"
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foreach pe $paths_latch {
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set is_latch [$pe is_latch_check]
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set is_check [$pe is_check]
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set is_output [$pe is_output_delay]
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puts " pin=[get_full_name [$pe pin]] latch=$is_latch check=$is_check output=$is_output slack=[$pe slack]"
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}
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puts "PASS: latch PathEnd queries"
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############################################################
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# report_checks with -fields for latch paths
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############################################################
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puts "--- report_checks with fields for latch ---"
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report_checks -path_delay max -fields {capacitance slew fanout input_pin}
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puts "PASS: latch fields"
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############################################################
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# report_checks to specific output with latch
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############################################################
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puts "--- report_checks to out1 (through latch) ---"
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report_checks -to [get_ports out1] -path_delay max -format full_clock
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puts "PASS: to out1 latch"
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puts "--- report_checks to out2 (through reg) ---"
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report_checks -to [get_ports out2] -path_delay max -format full_clock
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puts "PASS: to out2 reg"
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############################################################
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# Unconstrained paths
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############################################################
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puts "--- report_checks -unconstrained ---"
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report_checks -path_delay max -unconstrained
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puts "PASS: unconstrained"
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puts "--- report_checks -unconstrained -format short ---"
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report_checks -path_delay max -unconstrained -format short
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puts "PASS: unconstrained short"
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puts "--- report_checks -unconstrained -format end ---"
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report_checks -path_delay max -unconstrained -format end
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puts "PASS: unconstrained end"
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puts "--- report_checks -unconstrained -format summary ---"
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report_checks -path_delay max -unconstrained -format summary
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puts "PASS: unconstrained summary"
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############################################################
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# Latch borrow limit
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############################################################
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puts "--- set_max_time_borrow ---"
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catch {
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set_max_time_borrow 3.0 [get_clocks clk]
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report_checks -path_delay max -format full_clock
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}
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puts "PASS: max_time_borrow"
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############################################################
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# Now test with genclk design
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############################################################
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puts "--- Switch to genclk design ---"
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read_verilog search_genclk.v
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link_design search_genclk
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create_clock -name clk -period 10 [get_ports clk]
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create_generated_clock -name div_clk -source [get_pins clkbuf/Z] -divide_by 2 [get_pins div_reg/Q]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock div_clk 1.0 [get_ports out2]
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############################################################
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# Generated clock timing
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############################################################
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puts "--- genclk report_checks max ---"
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report_checks -path_delay max
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puts "PASS: genclk max"
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puts "--- genclk report_checks min ---"
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report_checks -path_delay min
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puts "PASS: genclk min"
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puts "--- genclk to div_clk domain ---"
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report_checks -to [get_ports out2] -path_delay max
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puts "PASS: genclk to out2"
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puts "--- genclk full_clock_expanded to div_clk domain ---"
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report_checks -to [get_ports out2] -format full_clock_expanded
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puts "PASS: genclk full_clock_expanded"
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puts "--- genclk full_clock to div_clk domain ---"
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report_checks -to [get_ports out2] -format full_clock
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puts "PASS: genclk full_clock"
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############################################################
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# multiply_by generated clock
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############################################################
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puts "--- delete_generated_clock and create multiply_by ---"
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delete_generated_clock div_clk
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create_generated_clock -name fast_clk -source [get_pins clkbuf/Z] -multiply_by 2 [get_pins div_reg/Q]
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set_output_delay -clock fast_clk 0.5 [get_ports out2]
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puts "--- multiply_by clock reports ---"
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report_checks -path_delay max
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report_checks -to [get_ports out2] -format full_clock_expanded
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puts "PASS: multiply_by genclk"
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############################################################
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# Generated clock with edges specification
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############################################################
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puts "--- delete and create with -edges ---"
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delete_generated_clock fast_clk
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create_generated_clock -name edge_clk -source [get_pins clkbuf/Z] -edges {1 2 3} [get_pins div_reg/Q]
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set_output_delay -clock edge_clk 0.5 [get_ports out2]
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report_checks -path_delay max
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report_checks -to [get_ports out2] -format full_clock_expanded
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report_clock_properties
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puts "PASS: edges genclk"
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############################################################
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# Clock groups with generated clocks
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############################################################
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puts "--- set_clock_groups ---"
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set_clock_groups -name cg1 -logically_exclusive -group {clk} -group {edge_clk}
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report_checks -path_delay max
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puts "PASS: clock_groups logically_exclusive"
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unset_clock_groups -logically_exclusive -name cg1
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puts "--- set_clock_groups -physically_exclusive ---"
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set_clock_groups -name cg2 -physically_exclusive -group {clk} -group {edge_clk}
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report_checks -path_delay max
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puts "PASS: clock_groups physically_exclusive"
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unset_clock_groups -physically_exclusive -name cg2
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puts "--- set_clock_groups -asynchronous ---"
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set_clock_groups -name cg3 -asynchronous -group {clk} -group {edge_clk}
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report_checks -path_delay max
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puts "PASS: clock_groups asynchronous"
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unset_clock_groups -asynchronous -name cg3
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############################################################
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# Clock latency/uncertainty on generated clock
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############################################################
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puts "--- clock_latency on genclk ---"
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set_clock_latency -source 0.15 [get_clocks edge_clk]
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set_clock_uncertainty 0.1 [get_clocks edge_clk]
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report_checks -path_delay max -to [get_ports out2]
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puts "PASS: genclk latency/uncertainty"
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############################################################
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# Clock skew with genclk
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############################################################
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puts "--- clock_skew with genclk ---"
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report_clock_skew -setup
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report_clock_skew -hold
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puts "PASS: genclk clock_skew"
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############################################################
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# Clock min period with genclk
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############################################################
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puts "--- clock_min_period genclk ---"
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report_clock_min_period
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report_clock_min_period -clocks edge_clk
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puts "PASS: genclk min_period"
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############################################################
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# check_setup with generated clocks
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############################################################
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puts "--- check_setup genclk ---"
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check_setup -verbose
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check_setup -verbose -generated_clocks
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puts "PASS: check_setup genclk"
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############################################################
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# report_check_types on genclk design
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############################################################
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puts "--- report_check_types on genclk ---"
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report_check_types -verbose
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puts "PASS: report_check_types genclk"
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############################################################
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# find_timing_paths with various options
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############################################################
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puts "--- find_timing_paths -unique_edges_to_endpoint ---"
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set ue_paths [find_timing_paths -unique_edges_to_endpoint -path_delay max -group_path_count 10 -endpoint_path_count 5]
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puts "unique edge paths: [llength $ue_paths]"
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puts "PASS: unique_edges"
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puts "--- find_timing_paths min_max ---"
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set mm_paths [find_timing_paths -path_delay min_max -group_path_count 5 -endpoint_path_count 3]
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puts "min_max paths: [llength $mm_paths]"
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puts "PASS: min_max paths"
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puts "ALL PASSED"
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