1230 lines
41 KiB
Plaintext
1230 lines
41 KiB
Plaintext
--- report_checks max (latch paths) ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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PASS: latch max
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--- report_checks min (latch paths) ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ latch1/G (DLH_X1)
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0.05 0.05 ^ latch1/Q (DLH_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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PASS: latch min
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--- report_checks -format full_clock ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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PASS: latch full_clock
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--- report_checks -format full_clock_expanded ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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PASS: latch full_clock_expanded
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--- report_checks -format short ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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PASS: latch short
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--- report_checks -format end ---
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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latch2/D (DLH_X1) 1.11 1.11 0.00 (MET)
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PASS: latch end
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--- report_checks -format summary ---
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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latch1/Q (DLH_X1) latch2/D (DLH_X1) 0.00
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PASS: latch summary
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--- report_checks -format slack_only ---
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Group Slack
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--------------------------------------------
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clk 0.00
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PASS: latch slack_only
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--- report_checks -format json ---
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{"checks": [
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{
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"type": "latch_check",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "latch1/Q",
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"endpoint": "latch2/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_latch",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 2.921e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "latch1",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch1/G",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "latch1",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch1/Q",
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"net": "n3",
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"arrival": 1.106e-09,
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"capacitance": 1.932e-15,
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"slew": 1.074e-11
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},
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{
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"instance": "latch2",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch2/D",
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"net": "n3",
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"arrival": 1.106e-09,
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"slew": 1.074e-11
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "search_latch",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 2.921e-15,
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"slew": 0.000e+00
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},
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{
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"instance": "latch2",
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"cell": "DLH_X1",
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"verilog_src": "",
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"pin": "latch2/G",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"data_arrival_time": 1.106e-09,
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"crpr": 0.000e+00,
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"margin": 5.497e-11,
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"required_time": 1.106e-09,
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"slack": 0.000e+00
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}
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]
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}
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PASS: latch json
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--- PathEnd queries on latch ---
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Found 18 paths
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pin=latch2/D latch=1 check=0 output=0 slack=0.0
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pin=latch2/D latch=1 check=0 output=0 slack=0.0
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pin=latch1/D latch=1 check=0 output=0 slack=0.0
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pin=latch1/D latch=1 check=0 output=0 slack=0.0
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pin=latch1/D latch=1 check=0 output=0 slack=0.0
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pin=latch1/D latch=1 check=0 output=0 slack=0.0
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pin=latch2/D latch=1 check=0 output=0 slack=0.0
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pin=latch2/D latch=1 check=0 output=0 slack=0.0
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pin=out1 latch=0 check=0 output=1 slack=6.813221542500969e-9
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pin=out1 latch=0 check=0 output=1 slack=6.868384527791704e-9
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pin=out2 latch=0 check=0 output=1 slack=7.899713772019368e-9
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pin=out2 latch=0 check=0 output=1 slack=7.901434173618327e-9
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pin=out1 latch=0 check=0 output=1 slack=7.923797618047956e-9
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pin=out1 latch=0 check=0 output=1 slack=7.934120027641711e-9
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pin=reg1/D latch=0 check=1 output=0 slack=8.852826915983769e-9
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pin=reg1/D latch=0 check=1 output=0 slack=8.88718165725777e-9
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pin=reg1/D latch=0 check=1 output=0 slack=9.902577424725223e-9
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pin=reg1/D latch=0 check=1 output=0 slack=9.91532278504792e-9
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PASS: latch PathEnd queries
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--- report_checks with fields for latch ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 0.00 1.05 v latch1/D (DLH_X1)
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2 1.93 0.01 0.06 1.11 v latch1/Q (DLH_X1)
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0.01 0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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-----------------------------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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-----------------------------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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PASS: latch fields
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--- report_checks to out1 (through latch) ---
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Startpoint: latch2 (positive level-sensitive latch clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.11 1.11 time given to startpoint
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0.00 1.11 v latch2/D (DLH_X1)
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0.06 1.16 v latch2/Q (DLH_X1)
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0.02 1.19 v buf2/Z (BUF_X1)
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0.00 1.19 v out1 (out)
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1.19 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-1.19 data arrival time
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---------------------------------------------------------
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6.81 slack (MET)
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PASS: to out1 latch
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--- report_checks to out2 (through reg) ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: to out2 reg
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--- report_checks -unconstrained ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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clk pulse width 5.00
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library setup time -0.05
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--------------------------------------------
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max time borrow 4.95
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actual time borrow 1.11
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--------------------------------------------
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PASS: unconstrained
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--- report_checks -unconstrained -format short ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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PASS: unconstrained short
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--- report_checks -unconstrained -format end ---
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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latch2/D (DLH_X1) 1.11 1.11 0.00 (MET)
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PASS: unconstrained end
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--- report_checks -unconstrained -format summary ---
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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latch1/Q (DLH_X1) latch2/D (DLH_X1) 0.00
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PASS: unconstrained summary
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--- set_max_time_borrow ---
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Startpoint: latch1 (positive level-sensitive latch clocked by clk)
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Endpoint: latch2 (positive level-sensitive latch clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.05 1.05 time given to startpoint
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0.00 1.05 v latch1/D (DLH_X1)
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0.06 1.11 v latch1/Q (DLH_X1)
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0.00 1.11 v latch2/D (DLH_X1)
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1.11 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ latch2/G (DLH_X1)
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1.11 1.11 time borrowed from endpoint
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1.11 data required time
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---------------------------------------------------------
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1.11 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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0.00 slack (MET)
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Time Borrowing Information
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--------------------------------------------
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user max time borrow 3.00
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actual time borrow 1.11
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--------------------------------------------
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PASS: max_time_borrow
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--- Switch to genclk design ---
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--- genclk report_checks max ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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|
|
20.00 20.00 clock div_clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
20.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 19.96 library setup time
|
|
19.96 data required time
|
|
---------------------------------------------------------
|
|
19.96 data required time
|
|
-10.08 data arrival time
|
|
---------------------------------------------------------
|
|
9.88 slack (MET)
|
|
|
|
|
|
PASS: genclk max
|
|
--- genclk report_checks min ---
|
|
Startpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ div_reg/CK (DFF_X1)
|
|
0.06 0.06 ^ div_reg/QN (DFF_X1)
|
|
0.00 0.06 ^ div_reg/D (DFF_X1)
|
|
0.06 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ div_reg/CK (DFF_X1)
|
|
0.01 0.01 library hold time
|
|
0.01 data required time
|
|
---------------------------------------------------------
|
|
0.01 data required time
|
|
-0.06 data arrival time
|
|
---------------------------------------------------------
|
|
0.05 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
|
|
Path Group: div_clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 v reg1/Q (DFF_X1)
|
|
0.00 0.08 v reg2/D (DFF_X1)
|
|
0.08 data arrival time
|
|
|
|
0.00 0.00 clock div_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg2/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
0.08 slack (MET)
|
|
|
|
|
|
PASS: genclk min
|
|
--- genclk to div_clk domain ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
|
|
Endpoint: out2 (output port clocked by div_clk)
|
|
Path Group: div_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock div_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
20.00 20.00 clock div_clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-1.00 19.00 output external delay
|
|
19.00 data required time
|
|
---------------------------------------------------------
|
|
19.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
18.90 slack (MET)
|
|
|
|
|
|
PASS: genclk to out2
|
|
--- genclk full_clock_expanded to div_clk domain ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
|
|
Endpoint: out2 (output port clocked by div_clk)
|
|
Path Group: div_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock div_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
20.00 20.00 clock div_clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-1.00 19.00 output external delay
|
|
19.00 data required time
|
|
---------------------------------------------------------
|
|
19.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
18.90 slack (MET)
|
|
|
|
|
|
PASS: genclk full_clock_expanded
|
|
--- genclk full_clock to div_clk domain ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
|
|
Endpoint: out2 (output port clocked by div_clk)
|
|
Path Group: div_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock div_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
20.00 20.00 clock div_clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-1.00 19.00 output external delay
|
|
19.00 data required time
|
|
---------------------------------------------------------
|
|
19.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
18.90 slack (MET)
|
|
|
|
|
|
PASS: genclk full_clock
|
|
--- delete_generated_clock and create multiply_by ---
|
|
--- multiply_by clock reports ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by fast_clk)
|
|
Endpoint: out2 (output port clocked by fast_clk)
|
|
Path Group: fast_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-0.50 4.50 output external delay
|
|
4.50 data required time
|
|
---------------------------------------------------------
|
|
4.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
4.40 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by fast_clk)
|
|
Endpoint: out2 (output port clocked by fast_clk)
|
|
Path Group: fast_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-0.50 4.50 output external delay
|
|
4.50 data required time
|
|
---------------------------------------------------------
|
|
4.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
4.40 slack (MET)
|
|
|
|
|
|
PASS: multiply_by genclk
|
|
--- delete and create with -edges ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-0.50 9.50 output external delay
|
|
9.50 data required time
|
|
---------------------------------------------------------
|
|
9.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
9.40 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-0.50 9.50 output external delay
|
|
9.50 data required time
|
|
---------------------------------------------------------
|
|
9.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
9.40 slack (MET)
|
|
|
|
|
|
Clock Period Waveform
|
|
----------------------------------------------------
|
|
clk 10.00 0.00 5.00
|
|
edge_clk 10.00 0.00 5.00 (generated)
|
|
PASS: edges genclk
|
|
--- set_clock_groups ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-0.50 9.50 output external delay
|
|
9.50 data required time
|
|
---------------------------------------------------------
|
|
9.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
9.40 slack (MET)
|
|
|
|
|
|
PASS: clock_groups logically_exclusive
|
|
--- set_clock_groups -physically_exclusive ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-0.50 9.50 output external delay
|
|
9.50 data required time
|
|
---------------------------------------------------------
|
|
9.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
9.40 slack (MET)
|
|
|
|
|
|
PASS: clock_groups physically_exclusive
|
|
--- set_clock_groups -asynchronous ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-0.50 9.50 output external delay
|
|
9.50 data required time
|
|
---------------------------------------------------------
|
|
9.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
9.40 slack (MET)
|
|
|
|
|
|
PASS: clock_groups asynchronous
|
|
--- clock_latency on genclk ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.15 0.15 clock network delay (ideal)
|
|
0.00 0.15 ^ reg2/CK (DFF_X1)
|
|
0.08 0.23 ^ reg2/Q (DFF_X1)
|
|
0.02 0.25 ^ buf3/Z (BUF_X1)
|
|
0.00 0.25 ^ out2 (out)
|
|
0.25 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.15 10.15 clock network delay (ideal)
|
|
-0.10 10.05 clock uncertainty
|
|
0.00 10.05 clock reconvergence pessimism
|
|
-0.50 9.55 output external delay
|
|
9.55 data required time
|
|
---------------------------------------------------------
|
|
9.55 data required time
|
|
-0.25 data arrival time
|
|
---------------------------------------------------------
|
|
9.30 slack (MET)
|
|
|
|
|
|
PASS: genclk latency/uncertainty
|
|
--- clock_skew with genclk ---
|
|
Clock clk
|
|
0.03 source latency div_reg/CK ^
|
|
-0.03 target latency div_reg/CK ^
|
|
0.00 CRPR
|
|
--------------
|
|
0.00 setup skew
|
|
|
|
Clock edge_clk
|
|
No launch/capture paths found.
|
|
|
|
Clock clk
|
|
0.03 source latency div_reg/CK ^
|
|
-0.03 target latency div_reg/CK ^
|
|
0.00 CRPR
|
|
--------------
|
|
0.00 hold skew
|
|
|
|
Clock edge_clk
|
|
No launch/capture paths found.
|
|
|
|
PASS: genclk clock_skew
|
|
--- clock_min_period genclk ---
|
|
clk period_min = 0.10 fmax = 9799.21
|
|
edge_clk period_min = 0.00 fmax = inf
|
|
edge_clk period_min = 0.00 fmax = inf
|
|
PASS: genclk min_period
|
|
--- check_setup genclk ---
|
|
PASS: check_setup genclk
|
|
--- report_check_types on genclk ---
|
|
Startpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ div_reg/CK (DFF_X1)
|
|
0.06 0.06 ^ div_reg/QN (DFF_X1)
|
|
0.00 0.06 ^ div_reg/D (DFF_X1)
|
|
0.06 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ div_reg/CK (DFF_X1)
|
|
0.01 0.01 library hold time
|
|
0.01 data required time
|
|
---------------------------------------------------------
|
|
0.01 data required time
|
|
-0.06 data arrival time
|
|
---------------------------------------------------------
|
|
0.05 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 v reg1/Q (DFF_X1)
|
|
0.00 0.08 v reg2/D (DFF_X1)
|
|
0.08 data arrival time
|
|
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.15 0.15 clock network delay (ideal)
|
|
0.10 0.25 clock uncertainty
|
|
0.00 0.25 clock reconvergence pessimism
|
|
0.25 ^ reg2/CK (DFF_X1)
|
|
0.00 0.25 library hold time
|
|
0.25 data required time
|
|
---------------------------------------------------------
|
|
0.25 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
-0.17 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by edge_clk)
|
|
Endpoint: out2 (output port clocked by edge_clk)
|
|
Path Group: edge_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock edge_clk (rise edge)
|
|
0.15 0.15 clock network delay (ideal)
|
|
0.00 0.15 ^ reg2/CK (DFF_X1)
|
|
0.08 0.23 ^ reg2/Q (DFF_X1)
|
|
0.02 0.25 ^ buf3/Z (BUF_X1)
|
|
0.00 0.25 ^ out2 (out)
|
|
0.25 data arrival time
|
|
|
|
10.00 10.00 clock edge_clk (rise edge)
|
|
0.15 10.15 clock network delay (ideal)
|
|
-0.10 10.05 clock uncertainty
|
|
0.00 10.05 clock reconvergence pessimism
|
|
-0.50 9.55 output external delay
|
|
9.55 data required time
|
|
---------------------------------------------------------
|
|
9.55 data required time
|
|
-0.25 data arrival time
|
|
---------------------------------------------------------
|
|
9.30 slack (MET)
|
|
|
|
|
|
max slew
|
|
|
|
Pin div_reg/QN v
|
|
max slew 0.20
|
|
slew 0.01
|
|
----------------
|
|
Slack 0.19 (MET)
|
|
|
|
max capacitance
|
|
|
|
Pin reg1/Q ^
|
|
max capacitance 60.73
|
|
capacitance 2.11
|
|
-----------------------
|
|
Slack 58.62 (MET)
|
|
|
|
Pin: div_reg/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.03 0.03 clock network delay (ideal)
|
|
0.00 0.03 div_reg/CK
|
|
0.03 open edge arrival time
|
|
|
|
5.00 5.00 clock clk (fall edge)
|
|
0.03 5.03 clock network delay (ideal)
|
|
0.00 5.03 div_reg/CK
|
|
0.00 5.03 clock reconvergence pessimism
|
|
5.03 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (high)
|
|
5.00 actual pulse width
|
|
---------------------------------------------------------
|
|
4.95 slack (MET)
|
|
|
|
|
|
PASS: report_check_types genclk
|
|
--- find_timing_paths -unique_edges_to_endpoint ---
|
|
unique edge paths: 12
|
|
PASS: unique_edges
|
|
--- find_timing_paths min_max ---
|
|
min_max paths: 18
|
|
PASS: min_max paths
|
|
ALL PASSED
|