127 lines
3.9 KiB
Tcl
127 lines
3.9 KiB
Tcl
# Test generated clocks
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_genclk.v
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link_design search_genclk
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# Create base clock
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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puts "--- create_generated_clock -divide_by 2 ---"
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create_generated_clock -name div_clk -source [get_pins clkbuf/Z] -divide_by 2 [get_pins div_reg/Q]
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set_output_delay -clock div_clk 1.0 [get_ports out2]
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puts "--- report_clock_properties ---"
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report_clock_properties
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puts "--- report_clock_properties div_clk ---"
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report_clock_properties div_clk
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puts "--- report_checks max ---"
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report_checks -path_delay max
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puts "--- report_checks min ---"
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report_checks -path_delay min
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puts "--- report_checks through generated clock domain ---"
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report_checks -to [get_ports out2] -path_delay max
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puts "--- report_checks -format full_clock for genclk path ---"
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report_checks -to [get_ports out2] -format full_clock
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puts "--- report_checks -format full_clock_expanded for genclk path ---"
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report_checks -to [get_ports out2] -format full_clock_expanded
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puts "--- report_clock_skew setup ---"
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report_clock_skew -setup
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puts "--- report_clock_skew hold ---"
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report_clock_skew -hold
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puts "--- report_clock_latency ---"
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report_clock_latency
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puts "--- report_clock_min_period ---"
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report_clock_min_period
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puts "--- report_clock_min_period -clocks ---"
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report_clock_min_period -clocks clk
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puts "--- report_clock_min_period div_clk ---"
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report_clock_min_period -clocks div_clk
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puts "--- check_setup for generated clocks ---"
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check_setup -verbose
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puts "--- check_setup -generated_clocks ---"
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check_setup -verbose -generated_clocks
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puts "--- report_check_types verbose ---"
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report_check_types -verbose
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puts "--- report_tns ---"
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report_tns -max
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puts "--- report_wns ---"
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report_wns -max
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puts "--- report_worst_slack ---"
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report_worst_slack -max
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puts "--- find_timing_paths through div_clk domain ---"
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set paths [find_timing_paths -to [get_ports out2] -path_delay max]
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puts "Found [llength $paths] paths to out2"
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puts "--- set_clock_groups -logically_exclusive ---"
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set_clock_groups -name clk_le -logically_exclusive -group {clk} -group {div_clk}
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report_checks -path_delay max
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puts "PASS: set_clock_groups -logically_exclusive applied"
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puts "--- unset_clock_groups ---"
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unset_clock_groups -logically_exclusive -name clk_le
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puts "--- set_clock_groups -asynchronous ---"
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set_clock_groups -name clk_async -asynchronous -group {clk} -group {div_clk}
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report_checks -path_delay max
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puts "PASS: set_clock_groups -asynchronous applied"
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puts "--- unset_clock_groups -asynchronous ---"
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unset_clock_groups -asynchronous -name clk_async
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puts "--- delete generated clock and create multiply_by ---"
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delete_generated_clock div_clk
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create_generated_clock -name fast_clk -source [get_pins clkbuf/Z] -multiply_by 2 [get_pins div_reg/Q]
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set_output_delay -clock fast_clk 0.5 [get_ports out2]
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puts "--- report_clock_properties after multiply_by ---"
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report_clock_properties
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puts "--- report_checks with multiply_by clock ---"
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report_checks -path_delay max
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puts "--- report_checks to out2 with fast_clk ---"
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report_checks -to [get_ports out2] -path_delay max
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puts "--- report_clock_min_period for fast_clk ---"
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report_clock_min_period -clocks fast_clk
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puts "--- set_clock_uncertainty on generated clock ---"
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set_clock_uncertainty 0.1 [get_clocks fast_clk]
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report_checks -path_delay max -to [get_ports out2]
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puts "PASS: clock_uncertainty on genclk applied"
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puts "--- set_clock_latency -source on generated clock ---"
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set_clock_latency -source 0.15 [get_clocks fast_clk]
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report_checks -path_delay max -to [get_ports out2]
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puts "PASS: clock_latency on genclk applied"
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puts "--- report_pulse_width_checks ---"
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report_pulse_width_checks
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puts "--- report_pulse_width_checks verbose ---"
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report_pulse_width_checks -verbose
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puts "ALL genclk tests PASSED"
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