837 lines
28 KiB
Plaintext
837 lines
28 KiB
Plaintext
--- create_generated_clock -divide_by 2 ---
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--- report_clock_properties ---
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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div_clk 20.00 0.00 10.00 (generated)
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--- report_clock_properties div_clk ---
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Clock Period Waveform
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----------------------------------------------------
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div_clk 20.00 0.00 10.00 (generated)
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--- report_checks max ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg2/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- report_checks min ---
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Startpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
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Endpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ div_reg/CK (DFF_X1)
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0.06 0.06 ^ div_reg/QN (DFF_X1)
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0.00 0.06 ^ div_reg/D (DFF_X1)
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0.06 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ div_reg/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Path Group: div_clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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--- report_checks through generated clock domain ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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---------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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18.90 slack (MET)
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--- report_checks -format full_clock for genclk path ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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---------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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18.90 slack (MET)
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--- report_checks -format full_clock_expanded for genclk path ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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---------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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18.90 slack (MET)
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--- report_clock_skew setup ---
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Clock clk
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0.03 source latency div_reg/CK ^
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-0.03 target latency div_reg/CK ^
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0.00 CRPR
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--------------
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0.00 setup skew
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Clock div_clk
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No launch/capture paths found.
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--- report_clock_skew hold ---
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Clock clk
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0.03 source latency div_reg/CK ^
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-0.03 target latency div_reg/CK ^
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0.00 CRPR
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--------------
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0.00 hold skew
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Clock div_clk
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No launch/capture paths found.
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.03 network latency div_reg/CK
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0.03 network latency div_reg/CK
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---------------
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0.03 0.03 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.03 network latency div_reg/CK
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0.03 network latency div_reg/CK
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---------------
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0.03 0.03 latency
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0.00 skew
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Clock div_clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg2/CK
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0.00 network latency reg2/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg2/CK
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0.00 network latency reg2/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_min_period ---
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clk period_min = 0.10 fmax = 9799.21
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div_clk period_min = 0.00 fmax = inf
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--- report_clock_min_period -clocks ---
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clk period_min = 0.10 fmax = 9799.21
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--- report_clock_min_period div_clk ---
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div_clk period_min = 0.00 fmax = inf
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--- check_setup for generated clocks ---
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--- check_setup -generated_clocks ---
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--- report_check_types verbose ---
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Startpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
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Endpoint: div_reg (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ div_reg/CK (DFF_X1)
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0.06 0.06 ^ div_reg/QN (DFF_X1)
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0.00 0.06 ^ div_reg/D (DFF_X1)
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0.06 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ div_reg/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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0.05 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Path Group: div_clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg2/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg2/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg2/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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max slew
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Pin div_reg/QN v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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max capacitance
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Pin reg1/Q ^
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max capacitance 60.73
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capacitance 2.11
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-----------------------
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Slack 58.62 (MET)
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Pin: div_reg/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.03 0.03 clock network delay (ideal)
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0.00 0.03 div_reg/CK
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0.03 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.03 5.03 clock network delay (ideal)
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0.00 5.03 div_reg/CK
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0.00 5.03 clock reconvergence pessimism
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5.03 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- report_tns ---
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tns max 0.00
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--- report_wns ---
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wns max 0.00
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--- report_worst_slack ---
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worst slack max 7.90
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--- find_timing_paths through div_clk domain ---
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Found 1 paths to out2
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--- set_clock_groups -logically_exclusive ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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---------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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18.90 slack (MET)
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PASS: set_clock_groups -logically_exclusive applied
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--- unset_clock_groups ---
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--- set_clock_groups -asynchronous ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
20.00 20.00 clock div_clk (rise edge)
|
|
0.00 20.00 clock network delay (ideal)
|
|
0.00 20.00 clock reconvergence pessimism
|
|
-1.00 19.00 output external delay
|
|
19.00 data required time
|
|
---------------------------------------------------------
|
|
19.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
18.90 slack (MET)
|
|
|
|
|
|
PASS: set_clock_groups -asynchronous applied
|
|
--- unset_clock_groups -asynchronous ---
|
|
--- delete generated clock and create multiply_by ---
|
|
--- report_clock_properties after multiply_by ---
|
|
Clock Period Waveform
|
|
----------------------------------------------------
|
|
clk 10.00 0.00 5.00
|
|
fast_clk 5.00 0.00 2.50 (generated)
|
|
--- report_checks with multiply_by clock ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.09 0.09 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by fast_clk)
|
|
Endpoint: out2 (output port clocked by fast_clk)
|
|
Path Group: fast_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-0.50 4.50 output external delay
|
|
4.50 data required time
|
|
---------------------------------------------------------
|
|
4.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
4.40 slack (MET)
|
|
|
|
|
|
--- report_checks to out2 with fast_clk ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by fast_clk)
|
|
Endpoint: out2 (output port clocked by fast_clk)
|
|
Path Group: fast_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-0.50 4.50 output external delay
|
|
4.50 data required time
|
|
---------------------------------------------------------
|
|
4.50 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
4.40 slack (MET)
|
|
|
|
|
|
--- report_clock_min_period for fast_clk ---
|
|
fast_clk period_min = 0.00 fmax = inf
|
|
--- set_clock_uncertainty on generated clock ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by fast_clk)
|
|
Endpoint: out2 (output port clocked by fast_clk)
|
|
Path Group: fast_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.02 0.10 ^ buf3/Z (BUF_X1)
|
|
0.00 0.10 ^ out2 (out)
|
|
0.10 data arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
-0.10 4.90 clock uncertainty
|
|
0.00 4.90 clock reconvergence pessimism
|
|
-0.50 4.40 output external delay
|
|
4.40 data required time
|
|
---------------------------------------------------------
|
|
4.40 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
4.30 slack (MET)
|
|
|
|
|
|
PASS: clock_uncertainty on genclk applied
|
|
--- set_clock_latency -source on generated clock ---
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by fast_clk)
|
|
Endpoint: out2 (output port clocked by fast_clk)
|
|
Path Group: fast_clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.15 0.15 clock network delay (ideal)
|
|
0.00 0.15 ^ reg2/CK (DFF_X1)
|
|
0.08 0.23 ^ reg2/Q (DFF_X1)
|
|
0.02 0.25 ^ buf3/Z (BUF_X1)
|
|
0.00 0.25 ^ out2 (out)
|
|
0.25 data arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.15 5.15 clock network delay (ideal)
|
|
-0.10 5.05 clock uncertainty
|
|
0.00 5.05 clock reconvergence pessimism
|
|
-0.50 4.55 output external delay
|
|
4.55 data required time
|
|
---------------------------------------------------------
|
|
4.55 data required time
|
|
-0.25 data arrival time
|
|
---------------------------------------------------------
|
|
4.30 slack (MET)
|
|
|
|
|
|
PASS: clock_latency on genclk applied
|
|
--- report_pulse_width_checks ---
|
|
Required Actual
|
|
Pin Width Width Slack
|
|
------------------------------------------------------------
|
|
reg2/CK (high) 0.05 2.50 2.45 (MET)
|
|
reg2/CK (low) 0.05 2.50 2.45 (MET)
|
|
div_reg/CK (high) 0.05 5.00 4.95 (MET)
|
|
reg1/CK (high) 0.05 5.00 4.95 (MET)
|
|
div_reg/CK (low) 0.05 5.00 4.95 (MET)
|
|
reg1/CK (low) 0.05 5.00 4.95 (MET)
|
|
|
|
--- report_pulse_width_checks verbose ---
|
|
Pin: reg2/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock fast_clk (rise edge)
|
|
0.15 0.15 clock network delay (ideal)
|
|
0.00 0.15 reg2/CK
|
|
0.15 open edge arrival time
|
|
|
|
2.50 2.50 clock fast_clk (fall edge)
|
|
0.15 2.65 clock network delay (ideal)
|
|
0.00 2.65 reg2/CK
|
|
0.00 2.65 clock reconvergence pessimism
|
|
2.65 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (high)
|
|
2.50 actual pulse width
|
|
---------------------------------------------------------
|
|
2.45 slack (MET)
|
|
|
|
Pin: reg2/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
2.50 2.50 clock fast_clk (fall edge)
|
|
0.15 2.65 clock network delay (ideal)
|
|
0.00 2.65 reg2/CK
|
|
2.65 open edge arrival time
|
|
|
|
5.00 5.00 clock fast_clk (rise edge)
|
|
0.15 5.15 clock network delay (ideal)
|
|
0.00 5.15 reg2/CK
|
|
0.00 5.15 clock reconvergence pessimism
|
|
5.15 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (low)
|
|
2.50 actual pulse width
|
|
---------------------------------------------------------
|
|
2.45 slack (MET)
|
|
|
|
Pin: div_reg/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.03 0.03 clock network delay (ideal)
|
|
0.00 0.03 div_reg/CK
|
|
0.03 open edge arrival time
|
|
|
|
5.00 5.00 clock clk (fall edge)
|
|
0.03 5.03 clock network delay (ideal)
|
|
0.00 5.03 div_reg/CK
|
|
0.00 5.03 clock reconvergence pessimism
|
|
5.03 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (high)
|
|
5.00 actual pulse width
|
|
---------------------------------------------------------
|
|
4.95 slack (MET)
|
|
|
|
Pin: reg1/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.03 0.03 clock network delay (ideal)
|
|
0.00 0.03 reg1/CK
|
|
0.03 open edge arrival time
|
|
|
|
5.00 5.00 clock clk (fall edge)
|
|
0.03 5.03 clock network delay (ideal)
|
|
0.00 5.03 reg1/CK
|
|
0.00 5.03 clock reconvergence pessimism
|
|
5.03 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (high)
|
|
5.00 actual pulse width
|
|
---------------------------------------------------------
|
|
4.95 slack (MET)
|
|
|
|
Pin: div_reg/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
5.00 5.00 clock clk (fall edge)
|
|
0.03 5.03 clock network delay (ideal)
|
|
0.00 5.03 div_reg/CK
|
|
5.03 open edge arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.03 10.03 clock network delay (ideal)
|
|
0.00 10.03 div_reg/CK
|
|
0.00 10.03 clock reconvergence pessimism
|
|
10.03 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (low)
|
|
5.00 actual pulse width
|
|
---------------------------------------------------------
|
|
4.95 slack (MET)
|
|
|
|
Pin: reg1/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
5.00 5.00 clock clk (fall edge)
|
|
0.03 5.03 clock network delay (ideal)
|
|
0.00 5.03 reg1/CK
|
|
5.03 open edge arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.03 10.03 clock network delay (ideal)
|
|
0.00 10.03 reg1/CK
|
|
0.00 10.03 clock reconvergence pessimism
|
|
10.03 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (low)
|
|
5.00 actual pulse width
|
|
---------------------------------------------------------
|
|
4.95 slack (MET)
|
|
|
|
|
|
ALL genclk tests PASSED
|