17 lines
388 B
Verilog
17 lines
388 B
Verilog
module search_gated_clk (clk, en, in1, out1);
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input clk, en, in1;
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output out1;
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wire n1, n2, gated_clk, n3;
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// Clock gating cell: AND gate gating the clock
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AND2_X1 clk_gate (.A1(clk), .A2(en), .ZN(gated_clk));
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// Logic
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BUF_X1 buf1 (.A(in1), .Z(n1));
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// Register on gated clock
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DFF_X1 reg1 (.D(n1), .CK(gated_clk), .Q(n2));
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BUF_X1 buf2 (.A(n2), .Z(out1));
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endmodule
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