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OpenSTA/search/test/search_gated_clk.ok

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--- gated clk basic timing ---
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ clk_gate/A1 (AND2_X1)
0.00 10.00 clock gating setup time
10.00 data required time
---------------------------------------------------------
10.00 data required time
-1.00 data arrival time
---------------------------------------------------------
9.00 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 v clk_gate/A1 (AND2_X1)
0.00 5.00 clock gating hold time
5.00 data required time
---------------------------------------------------------
5.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-4.00 slack (VIOLATED)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in1 (in)
0.02 1.02 ^ buf1/Z (BUF_X1)
0.00 1.02 ^ reg1/D (DFF_X1)
1.02 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.02 data arrival time
---------------------------------------------------------
1.01 slack (MET)
PASS: gated clk basic
--- gated_clk_checks_enabled ---
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ clk_gate/A1 (AND2_X1)
0.00 10.00 clock gating setup time
10.00 data required time
---------------------------------------------------------
10.00 data required time
-1.00 data arrival time
---------------------------------------------------------
9.00 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 v clk_gate/A1 (AND2_X1)
0.00 5.00 clock gating hold time
5.00 data required time
---------------------------------------------------------
5.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-4.00 slack (VIOLATED)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in1 (in)
0.02 1.02 ^ buf1/Z (BUF_X1)
0.00 1.02 ^ reg1/D (DFF_X1)
1.02 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.02 data arrival time
---------------------------------------------------------
1.01 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 v clk_gate/A1 (AND2_X1)
0.00 5.00 clock gating hold time
5.00 data required time
---------------------------------------------------------
5.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-4.00 slack (VIOLATED)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in1 (in)
0.02 1.02 ^ buf1/Z (BUF_X1)
0.00 1.02 ^ reg1/D (DFF_X1)
1.02 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.02 data arrival time
---------------------------------------------------------
1.01 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ clk_gate/A1 (AND2_X1)
0.00 10.00 clock gating setup time
10.00 data required time
---------------------------------------------------------
10.00 data required time
-1.00 data arrival time
---------------------------------------------------------
9.00 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
max slew
Pin reg1/QN v
max slew 0.20
slew 0.01
----------------
Slack 0.19 (MET)
max capacitance
Pin buf1/Z ^
max capacitance 60.65
capacitance 1.14
-----------------------
Slack 59.51 (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.02 0.02 clock network delay (ideal)
0.00 0.02 reg1/CK
0.02 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.02 5.02 clock network delay (ideal)
0.00 5.02 reg1/CK
0.00 5.02 clock reconvergence pessimism
5.02 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
PASS: gated_clk_checks_enabled
--- propagate_gated_clock_enable ---
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ clk_gate/A1 (AND2_X1)
0.00 10.00 clock gating setup time
10.00 data required time
---------------------------------------------------------
10.00 data required time
-1.00 data arrival time
---------------------------------------------------------
9.00 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 v clk_gate/A1 (AND2_X1)
0.00 5.00 clock gating hold time
5.00 data required time
---------------------------------------------------------
5.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-4.00 slack (VIOLATED)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in1 (in)
0.02 1.02 ^ buf1/Z (BUF_X1)
0.00 1.02 ^ reg1/D (DFF_X1)
1.02 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.02 data arrival time
---------------------------------------------------------
1.01 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
5.00 5.00 clock clk (fall edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
5.00 v clk_gate/A1 (AND2_X1)
0.00 5.00 clock gating hold time
5.00 data required time
---------------------------------------------------------
5.00 data required time
-1.00 data arrival time
---------------------------------------------------------
-4.00 slack (VIOLATED)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in1 (in)
0.02 1.02 ^ buf1/Z (BUF_X1)
0.00 1.02 ^ reg1/D (DFF_X1)
1.02 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.02 data arrival time
---------------------------------------------------------
1.01 slack (MET)
Startpoint: en (input port clocked by clk)
Endpoint: clk_gate (rising clock gating-check end-point clocked by clk)
Path Group: gated clock
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ en (in)
0.00 1.00 ^ clk_gate/A2 (AND2_X1)
1.00 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ clk_gate/A1 (AND2_X1)
0.00 10.00 clock gating setup time
10.00 data required time
---------------------------------------------------------
10.00 data required time
-1.00 data arrival time
---------------------------------------------------------
9.00 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
max slew
Pin reg1/QN v
max slew 0.20
slew 0.01
----------------
Slack 0.19 (MET)
max capacitance
Pin buf1/Z ^
max capacitance 60.65
capacitance 1.14
-----------------------
Slack 59.51 (MET)
Pin: reg1/CK
Check: sequential_clock_pulse_width
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.02 0.02 clock network delay (ideal)
0.00 0.02 reg1/CK
0.02 open edge arrival time
5.00 5.00 clock clk (fall edge)
0.02 5.02 clock network delay (ideal)
0.00 5.02 reg1/CK
0.00 5.02 clock reconvergence pessimism
5.02 close edge arrival time
---------------------------------------------------------
0.05 required pulse width (high)
5.00 actual pulse width
---------------------------------------------------------
4.95 slack (MET)
PASS: propagate_gated_clock_enable
--- Gated clk with inferred clock gating ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
PASS: inferred clock gating
--- report_checks format full_clock with gated clk ---
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.02 0.10 ^ buf2/Z (BUF_X1)
0.00 0.10 ^ out1 (out)
0.10 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.00 8.00 output external delay
8.00 data required time
---------------------------------------------------------
8.00 data required time
-0.10 data arrival time
---------------------------------------------------------
7.90 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 ^ input external delay
0.00 1.00 ^ in1 (in)
0.02 1.02 ^ buf1/Z (BUF_X1)
0.00 1.02 ^ reg1/D (DFF_X1)
1.02 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-1.02 data arrival time
---------------------------------------------------------
1.01 slack (MET)
PASS: gated clk report formats
--- find_timing_paths with gated clk ---
Found 4 paths
is_gated_clock: 0
is_check: 0
pin: out1
is_gated_clock: 0
is_check: 0
pin: out1
is_gated_clock: 0
is_check: 1
pin: reg1/D
is_gated_clock: 0
is_check: 1
pin: reg1/D
PASS: find_timing_paths gated clk
ALL PASSED
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