1688 lines
51 KiB
Plaintext
1688 lines
51 KiB
Plaintext
--- CRPR setup with two clocks ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.15 ^ reg2/Q (DFF_X1)
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0.02 0.17 ^ buf3/Z (BUF_X1)
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0.00 0.17 ^ out1 (out)
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0.17 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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7.33 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk2 (in)
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0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
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0.00 0.02 ^ reg3/CK (DFF_X1)
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0.09 0.11 ^ reg3/Q (DFF_X1)
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0.02 0.13 ^ buf4/Z (BUF_X1)
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0.00 0.13 ^ out2 (out)
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0.13 data arrival time
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8.00 8.00 clock clk2 (rise edge)
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0.00 8.00 clock network delay (propagated)
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-0.40 7.60 clock uncertainty
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0.00 7.60 clock reconvergence pessimism
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-2.00 5.60 output external delay
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5.60 data required time
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---------------------------------------------------------
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5.60 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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5.47 slack (MET)
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PASS: CRPR setup two clocks
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--- CRPR hold with two clocks ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.02 0.02 ^ ck1buf1/Z (CLKBUF_X1)
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0.00 0.02 ^ reg1/CK (DFF_X1)
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0.08 0.11 ^ reg1/Q (DFF_X1)
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0.02 0.13 ^ buf2/Z (BUF_X1)
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0.00 0.13 ^ reg2/D (DFF_X1)
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0.13 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.30 0.35 clock uncertainty
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0.00 0.35 clock reconvergence pessimism
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0.01 0.36 library hold time
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0.36 data required time
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---------------------------------------------------------
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0.36 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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-0.23 slack (VIOLATED)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk2 (in)
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0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
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0.00 0.02 ^ reg3/CK (DFF_X1)
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0.08 0.10 v reg3/Q (DFF_X1)
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0.02 0.12 v buf4/Z (BUF_X1)
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0.00 0.12 v out2 (out)
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0.12 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.20 0.20 clock uncertainty
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0.00 0.20 clock reconvergence pessimism
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-2.00 -1.80 output external delay
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-1.80 data required time
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---------------------------------------------------------
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-1.80 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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PASS: CRPR hold two clocks
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--- CRPR same_pin mode ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.15 ^ reg2/Q (DFF_X1)
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0.02 0.17 ^ buf3/Z (BUF_X1)
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0.00 0.17 ^ out1 (out)
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0.17 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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7.33 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk2 (in)
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0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
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0.00 0.02 ^ reg3/CK (DFF_X1)
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0.09 0.11 ^ reg3/Q (DFF_X1)
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0.02 0.13 ^ buf4/Z (BUF_X1)
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0.00 0.13 ^ out2 (out)
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0.13 data arrival time
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8.00 8.00 clock clk2 (rise edge)
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0.00 8.00 clock network delay (propagated)
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-0.40 7.60 clock uncertainty
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0.00 7.60 clock reconvergence pessimism
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-2.00 5.60 output external delay
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5.60 data required time
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---------------------------------------------------------
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5.60 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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5.47 slack (MET)
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PASS: CRPR same_pin
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--- CRPR same_transition mode ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.15 ^ reg2/Q (DFF_X1)
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0.02 0.17 ^ buf3/Z (BUF_X1)
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0.00 0.17 ^ out1 (out)
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0.17 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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7.33 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk2 (in)
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0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
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0.00 0.02 ^ reg3/CK (DFF_X1)
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0.09 0.11 ^ reg3/Q (DFF_X1)
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0.02 0.13 ^ buf4/Z (BUF_X1)
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0.00 0.13 ^ out2 (out)
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0.13 data arrival time
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8.00 8.00 clock clk2 (rise edge)
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0.00 8.00 clock network delay (propagated)
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-0.40 7.60 clock uncertainty
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0.00 7.60 clock reconvergence pessimism
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-2.00 5.60 output external delay
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5.60 data required time
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---------------------------------------------------------
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5.60 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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5.47 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.02 0.02 ^ ck1buf1/Z (CLKBUF_X1)
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0.00 0.02 ^ reg1/CK (DFF_X1)
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0.08 0.11 ^ reg1/Q (DFF_X1)
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0.02 0.13 ^ buf2/Z (BUF_X1)
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0.00 0.13 ^ reg2/D (DFF_X1)
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0.13 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.30 0.35 clock uncertainty
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0.00 0.35 clock reconvergence pessimism
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0.01 0.36 library hold time
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0.36 data required time
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---------------------------------------------------------
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0.36 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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-0.23 slack (VIOLATED)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk2 (in)
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0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
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0.00 0.02 ^ reg3/CK (DFF_X1)
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0.08 0.10 v reg3/Q (DFF_X1)
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0.02 0.12 v buf4/Z (BUF_X1)
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0.00 0.12 v out2 (out)
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0.12 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.20 0.20 clock uncertainty
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0.00 0.20 clock reconvergence pessimism
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-2.00 -1.80 output external delay
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-1.80 data required time
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---------------------------------------------------------
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-1.80 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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PASS: CRPR same_transition
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--- CRPR disabled ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk1 (in)
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0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.15 ^ reg2/Q (DFF_X1)
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0.02 0.17 ^ buf3/Z (BUF_X1)
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0.00 0.17 ^ out1 (out)
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0.17 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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7.33 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk2 (in)
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0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
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0.00 0.02 ^ reg3/CK (DFF_X1)
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0.09 0.11 ^ reg3/Q (DFF_X1)
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0.02 0.13 ^ buf4/Z (BUF_X1)
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0.00 0.13 ^ out2 (out)
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0.13 data arrival time
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8.00 8.00 clock clk2 (rise edge)
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0.00 8.00 clock network delay (propagated)
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-0.40 7.60 clock uncertainty
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-2.00 5.60 output external delay
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5.60 data required time
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---------------------------------------------------------
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5.60 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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5.47 slack (MET)
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PASS: CRPR disable/enable
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--- report_clock_skew setup/hold ---
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Clock clk1
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.50 clock uncertainty
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-0.00 CRPR
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--------------
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0.48 setup skew
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Clock clk2
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No launch/capture paths found.
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Clock clk1
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0.02 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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-0.30 clock uncertainty
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-0.00 CRPR
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--------------
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-0.33 hold skew
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Clock clk2
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No launch/capture paths found.
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PASS: clock_skew
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--- report_clock_latency ---
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Clock clk1
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rise -> rise
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.02 0.05 latency
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0.03 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.02 0.05 latency
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0.03 skew
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Clock clk2
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rise -> rise
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min max
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0.00 0.00 source latency
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0.02 network latency reg3/CK
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0.02 network latency reg3/CK
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---------------
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0.02 0.02 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg3/CK
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0.02 network latency reg3/CK
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---------------
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0.02 0.02 latency
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0.00 skew
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PASS: clock_latency
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--- find_timing_paths with CRPR ---
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Found 7 paths
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slack=7.334127083424846e-9 crpr=0.0 pin=out1
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slack=7.3365340469422335e-9 crpr=0.0 pin=out1
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slack=8.43751646328883e-9 crpr=0.0 pin=reg1/D
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slack=8.439848819818963e-9 crpr=0.0 pin=reg1/D
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slack=8.446774835135784e-9 crpr=0.0 pin=reg1/D
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slack=5.46777734200532e-9 crpr=0.0 pin=out2
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slack=5.469566577431806e-9 crpr=0.0 pin=out2
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PASS: find_timing_paths CRPR
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--- find_timing_paths min with CRPR ---
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Found 7 hold paths
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slack=-2.327258247225572e-10 crpr=-2.547686020482054e-12
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slack=-2.3130949933225509e-10 crpr=-2.547686020482054e-12
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slack=7.07958414114529e-10 crpr=-0.0
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slack=7.091847664675299e-10 crpr=-0.0
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slack=7.135160240423488e-10 crpr=-0.0
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slack=1.918010639201384e-9 crpr=-0.0
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slack=1.9196295664158924e-9 crpr=-0.0
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PASS: find_timing_paths min CRPR
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--- worst_slack by clock ---
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worst_slack max: 5.46777734200532e-9
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worst_slack min: -2.327258247225572e-10
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PASS: worst_slack with two clocks
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--- total_negative_slack ---
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tns max: 0.0
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tns min: -2.327258247225572e-10
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PASS: tns with two clocks
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--- report_tns/wns ---
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tns max 0.00
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wns max 0.00
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worst slack max 5.47
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worst slack min -0.23
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PASS: report_tns/wns
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--- report_check_types ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 ^ reg1/CK (DFF_X1)
|
|
0.08 0.11 ^ reg1/Q (DFF_X1)
|
|
0.02 0.13 ^ buf2/Z (BUF_X1)
|
|
0.00 0.13 ^ reg2/D (DFF_X1)
|
|
0.13 data arrival time
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.05 0.05 clock network delay (propagated)
|
|
0.30 0.35 clock uncertainty
|
|
0.00 0.35 clock reconvergence pessimism
|
|
0.35 ^ reg2/CK (DFF_X1)
|
|
0.01 0.36 library hold time
|
|
0.36 data required time
|
|
---------------------------------------------------------
|
|
0.36 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
-0.23 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.08 0.10 v reg3/Q (DFF_X1)
|
|
0.02 0.12 v buf4/Z (BUF_X1)
|
|
0.00 0.12 v out2 (out)
|
|
0.12 data arrival time
|
|
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock network delay (propagated)
|
|
0.20 0.20 clock uncertainty
|
|
0.00 0.20 clock reconvergence pessimism
|
|
-2.00 -1.80 output external delay
|
|
-1.80 data required time
|
|
---------------------------------------------------------
|
|
-1.80 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
1.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: out1 (output port clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.05 0.05 clock network delay (propagated)
|
|
0.00 0.05 ^ reg2/CK (DFF_X1)
|
|
0.09 0.15 ^ reg2/Q (DFF_X1)
|
|
0.02 0.17 ^ buf3/Z (BUF_X1)
|
|
0.00 0.17 ^ out1 (out)
|
|
0.17 data arrival time
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock network delay (propagated)
|
|
-0.50 9.50 clock uncertainty
|
|
0.00 9.50 clock reconvergence pessimism
|
|
-2.00 7.50 output external delay
|
|
7.50 data required time
|
|
---------------------------------------------------------
|
|
7.50 data required time
|
|
-0.17 data arrival time
|
|
---------------------------------------------------------
|
|
7.33 slack (MET)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.09 0.11 ^ reg3/Q (DFF_X1)
|
|
0.02 0.13 ^ buf4/Z (BUF_X1)
|
|
0.00 0.13 ^ out2 (out)
|
|
0.13 data arrival time
|
|
|
|
8.00 8.00 clock clk2 (rise edge)
|
|
0.00 8.00 clock network delay (propagated)
|
|
-0.40 7.60 clock uncertainty
|
|
0.00 7.60 clock reconvergence pessimism
|
|
-2.00 5.60 output external delay
|
|
5.60 data required time
|
|
---------------------------------------------------------
|
|
5.60 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
5.47 slack (MET)
|
|
|
|
|
|
max slew
|
|
|
|
Pin reg1/QN v
|
|
max slew 0.20
|
|
slew 0.01
|
|
----------------
|
|
Slack 0.19 (MET)
|
|
|
|
max capacitance
|
|
|
|
Pin reg2/Q ^
|
|
max capacitance 60.73
|
|
capacitance 2.11
|
|
-----------------------
|
|
Slack 58.62 (MET)
|
|
|
|
Pin: reg3/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 reg3/CK
|
|
0.02 open edge arrival time
|
|
|
|
4.00 4.00 clock clk2 (fall edge)
|
|
0.02 4.02 clock network delay (propagated)
|
|
0.00 4.02 reg3/CK
|
|
0.00 4.02 clock reconvergence pessimism
|
|
4.02 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (high)
|
|
4.00 actual pulse width
|
|
---------------------------------------------------------
|
|
3.94 slack (MET)
|
|
|
|
|
|
PASS: check_types
|
|
--- check_setup ---
|
|
PASS: check_setup
|
|
--- Now set_data_check for skew testing ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock source latency
|
|
0.00 10.00 ^ clk1 (in)
|
|
0.03 10.03 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.00 10.03 ^ reg1/CK (DFF_X1)
|
|
0.09 10.12 ^ reg1/Q (DFF_X1)
|
|
0.02 10.14 ^ buf2/Z (BUF_X1)
|
|
0.00 10.14 ^ reg2/D (DFF_X1)
|
|
10.14 data arrival time
|
|
|
|
5.00 5.00 clock clk1 (fall edge)
|
|
0.00 5.00 clock source latency
|
|
0.00 5.00 v clk1 (in)
|
|
0.02 5.02 v ck1buf1/Z (CLKBUF_X1)
|
|
0.00 5.02 v reg1/CK (DFF_X1)
|
|
-0.50 4.52 clock uncertainty
|
|
0.00 4.52 clock reconvergence pessimism
|
|
-0.10 4.42 data check setup time
|
|
4.42 data required time
|
|
---------------------------------------------------------
|
|
4.42 data required time
|
|
-10.14 data arrival time
|
|
---------------------------------------------------------
|
|
-5.72 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk2 (in)
|
|
0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.09 0.11 ^ reg3/Q (DFF_X1)
|
|
0.02 0.13 ^ buf4/Z (BUF_X1)
|
|
0.00 0.13 ^ out2 (out)
|
|
0.13 data arrival time
|
|
|
|
8.00 8.00 clock clk2 (rise edge)
|
|
0.00 8.00 clock network delay (propagated)
|
|
-0.40 7.60 clock uncertainty
|
|
0.00 7.60 clock reconvergence pessimism
|
|
-2.00 5.60 output external delay
|
|
5.60 data required time
|
|
---------------------------------------------------------
|
|
5.60 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
5.47 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk1 (in)
|
|
0.02 0.02 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.00 0.02 ^ reg1/CK (DFF_X1)
|
|
0.08 0.11 ^ reg1/Q (DFF_X1)
|
|
0.02 0.13 ^ buf2/Z (BUF_X1)
|
|
0.00 0.13 ^ reg2/D (DFF_X1)
|
|
0.13 data arrival time
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk1 (in)
|
|
0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
|
|
0.00 0.05 ^ reg2/CK (DFF_X1)
|
|
0.30 0.35 clock uncertainty
|
|
0.00 0.35 clock reconvergence pessimism
|
|
0.01 0.36 library hold time
|
|
0.36 data required time
|
|
---------------------------------------------------------
|
|
0.36 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
-0.23 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk2 (in)
|
|
0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.08 0.10 v reg3/Q (DFF_X1)
|
|
0.02 0.12 v buf4/Z (BUF_X1)
|
|
0.00 0.12 v out2 (out)
|
|
0.12 data arrival time
|
|
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock network delay (propagated)
|
|
0.20 0.20 clock uncertainty
|
|
0.00 0.20 clock reconvergence pessimism
|
|
-2.00 -1.80 output external delay
|
|
-1.80 data required time
|
|
---------------------------------------------------------
|
|
-1.80 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
1.92 slack (MET)
|
|
|
|
|
|
data_check constraints applied
|
|
PASS: data_check constraints
|
|
--- report_checks with various formats ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.03 10.03 clock network delay (propagated)
|
|
0.00 10.03 ^ reg1/CK (DFF_X1)
|
|
0.09 10.12 ^ reg1/Q (DFF_X1)
|
|
0.02 10.14 ^ buf2/Z (BUF_X1)
|
|
0.00 10.14 ^ reg2/D (DFF_X1)
|
|
10.14 data arrival time
|
|
|
|
5.00 5.00 clock clk1 (fall edge)
|
|
0.02 5.02 clock network delay (propagated)
|
|
-0.50 4.52 clock uncertainty
|
|
0.00 4.52 clock reconvergence pessimism
|
|
4.52 v reg1/CK (DFF_X1)
|
|
-0.10 4.42 data check setup time
|
|
4.42 data required time
|
|
---------------------------------------------------------
|
|
4.42 data required time
|
|
-10.14 data arrival time
|
|
---------------------------------------------------------
|
|
-5.72 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.09 0.11 ^ reg3/Q (DFF_X1)
|
|
0.02 0.13 ^ buf4/Z (BUF_X1)
|
|
0.00 0.13 ^ out2 (out)
|
|
0.13 data arrival time
|
|
|
|
8.00 8.00 clock clk2 (rise edge)
|
|
0.00 8.00 clock network delay (propagated)
|
|
-0.40 7.60 clock uncertainty
|
|
0.00 7.60 clock reconvergence pessimism
|
|
-2.00 5.60 output external delay
|
|
5.60 data required time
|
|
---------------------------------------------------------
|
|
5.60 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
5.47 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock source latency
|
|
0.00 10.00 ^ clk1 (in)
|
|
0.03 10.03 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.00 10.03 ^ reg1/CK (DFF_X1)
|
|
0.09 10.12 ^ reg1/Q (DFF_X1)
|
|
0.02 10.14 ^ buf2/Z (BUF_X1)
|
|
0.00 10.14 ^ reg2/D (DFF_X1)
|
|
10.14 data arrival time
|
|
|
|
5.00 5.00 clock clk1 (fall edge)
|
|
0.00 5.00 clock source latency
|
|
0.00 5.00 v clk1 (in)
|
|
0.02 5.02 v ck1buf1/Z (CLKBUF_X1)
|
|
0.00 5.02 v reg1/CK (DFF_X1)
|
|
-0.50 4.52 clock uncertainty
|
|
0.00 4.52 clock reconvergence pessimism
|
|
-0.10 4.42 data check setup time
|
|
4.42 data required time
|
|
---------------------------------------------------------
|
|
4.42 data required time
|
|
-10.14 data arrival time
|
|
---------------------------------------------------------
|
|
-5.72 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk2 (in)
|
|
0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.09 0.11 ^ reg3/Q (DFF_X1)
|
|
0.02 0.13 ^ buf4/Z (BUF_X1)
|
|
0.00 0.13 ^ out2 (out)
|
|
0.13 data arrival time
|
|
|
|
8.00 8.00 clock clk2 (rise edge)
|
|
0.00 8.00 clock network delay (propagated)
|
|
-0.40 7.60 clock uncertainty
|
|
0.00 7.60 clock reconvergence pessimism
|
|
-2.00 5.60 output external delay
|
|
5.60 data required time
|
|
---------------------------------------------------------
|
|
5.60 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
5.47 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
|
|
max_delay/setup group clk1
|
|
|
|
Required Actual
|
|
Endpoint Delay Delay Slack
|
|
------------------------------------------------------------
|
|
reg2/D (DFF_X1) 4.42 10.14 -5.72 (VIOLATED)
|
|
|
|
max_delay/setup group clk2
|
|
|
|
Required Actual
|
|
Endpoint Delay Delay Slack
|
|
------------------------------------------------------------
|
|
out2 (output) 5.60 0.13 5.47 (MET)
|
|
|
|
Group Slack
|
|
--------------------------------------------
|
|
clk1 -5.72
|
|
clk2 5.47
|
|
|
|
Startpoint Endpoint Slack
|
|
--------------------------------------------------------------------------------
|
|
reg1/Q (DFF_X1) reg2/D (DFF_X1) -5.72
|
|
reg3/Q (search_crpr_data_checks) out2 (output) 5.47
|
|
|
|
{"checks": [
|
|
{
|
|
"type": "data_check",
|
|
"path_group": "clk1",
|
|
"path_type": "max",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "reg2/D",
|
|
"source_clock": "clk1",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "clk1",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 7.798e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/A",
|
|
"net": "clk1",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/Z",
|
|
"net": "clk1_buf1",
|
|
"arrival": 2.675e-11,
|
|
"capacitance": 1.729e-15,
|
|
"slew": 8.079e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk1_buf1",
|
|
"arrival": 2.675e-11,
|
|
"slew": 8.079e-12
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 1.182e-10,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.316e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 1.182e-10,
|
|
"slew": 7.316e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "n4",
|
|
"arrival": 1.389e-10,
|
|
"capacitance": 1.140e-15,
|
|
"slew": 5.953e-12
|
|
},
|
|
{
|
|
"instance": "reg2",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg2/D",
|
|
"net": "n4",
|
|
"arrival": 1.389e-10,
|
|
"slew": 5.953e-12
|
|
}
|
|
],
|
|
"target_clock": "clk1",
|
|
"target_clock_edge": "fall",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "clk1",
|
|
"arrival": 5.000e-09,
|
|
"capacitance": 6.992e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/A",
|
|
"net": "clk1",
|
|
"arrival": 5.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/Z",
|
|
"net": "clk1_buf1",
|
|
"arrival": 5.023e-09,
|
|
"capacitance": 1.556e-15,
|
|
"slew": 7.246e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk1_buf1",
|
|
"arrival": 5.023e-09,
|
|
"slew": 7.246e-12
|
|
}
|
|
],
|
|
"data_arrival_time": 1.014e-08,
|
|
"crpr": 0.000e+00,
|
|
"margin": 1.000e-10,
|
|
"required_time": 4.423e-09,
|
|
"slack": -5.716e-09
|
|
},
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk2",
|
|
"path_type": "max",
|
|
"startpoint": "reg3/Q",
|
|
"endpoint": "out2",
|
|
"source_clock": "clk2",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "clk2",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 7.798e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck2buf",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck2buf/A",
|
|
"net": "clk2",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck2buf",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck2buf/Z",
|
|
"net": "clk2_buf",
|
|
"arrival": 2.404e-11,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 6.551e-12
|
|
},
|
|
{
|
|
"instance": "reg3",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg3/CK",
|
|
"net": "clk2_buf",
|
|
"arrival": 2.404e-11,
|
|
"slew": 6.551e-12
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg3",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg3/Q",
|
|
"net": "n6",
|
|
"arrival": 1.148e-10,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.316e-12
|
|
},
|
|
{
|
|
"instance": "buf4",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf4/A",
|
|
"net": "n6",
|
|
"arrival": 1.148e-10,
|
|
"slew": 7.316e-12
|
|
},
|
|
{
|
|
"instance": "buf4",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf4/Z",
|
|
"net": "out2",
|
|
"arrival": 1.322e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.638e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "out2",
|
|
"arrival": 1.322e-10,
|
|
"slew": 3.638e-12
|
|
}
|
|
],
|
|
"target_clock": "clk2",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.322e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 5.600e-09,
|
|
"slack": 5.468e-09
|
|
}
|
|
]
|
|
}
|
|
PASS: all formats with two clocks
|
|
--- report_checks min formats ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 ^ reg1/CK (DFF_X1)
|
|
0.08 0.11 ^ reg1/Q (DFF_X1)
|
|
0.02 0.13 ^ buf2/Z (BUF_X1)
|
|
0.00 0.13 ^ reg2/D (DFF_X1)
|
|
0.13 data arrival time
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.05 0.05 clock network delay (propagated)
|
|
0.30 0.35 clock uncertainty
|
|
0.00 0.35 clock reconvergence pessimism
|
|
0.35 ^ reg2/CK (DFF_X1)
|
|
0.01 0.36 library hold time
|
|
0.36 data required time
|
|
---------------------------------------------------------
|
|
0.36 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
-0.23 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.08 0.10 v reg3/Q (DFF_X1)
|
|
0.02 0.12 v buf4/Z (BUF_X1)
|
|
0.00 0.12 v out2 (out)
|
|
0.12 data arrival time
|
|
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock network delay (propagated)
|
|
0.20 0.20 clock uncertainty
|
|
0.00 0.20 clock reconvergence pessimism
|
|
-2.00 -1.80 output external delay
|
|
-1.80 data required time
|
|
---------------------------------------------------------
|
|
-1.80 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
1.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk1 (in)
|
|
0.02 0.02 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.00 0.02 ^ reg1/CK (DFF_X1)
|
|
0.08 0.11 ^ reg1/Q (DFF_X1)
|
|
0.02 0.13 ^ buf2/Z (BUF_X1)
|
|
0.00 0.13 ^ reg2/D (DFF_X1)
|
|
0.13 data arrival time
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk1 (in)
|
|
0.03 0.03 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.03 0.05 ^ ck1buf2/Z (CLKBUF_X1)
|
|
0.00 0.05 ^ reg2/CK (DFF_X1)
|
|
0.30 0.35 clock uncertainty
|
|
0.00 0.35 clock reconvergence pessimism
|
|
0.01 0.36 library hold time
|
|
0.36 data required time
|
|
---------------------------------------------------------
|
|
0.36 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
-0.23 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
0.00 0.00 ^ clk2 (in)
|
|
0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
|
|
0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
0.08 0.10 v reg3/Q (DFF_X1)
|
|
0.02 0.12 v buf4/Z (BUF_X1)
|
|
0.00 0.12 v out2 (out)
|
|
0.12 data arrival time
|
|
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock network delay (propagated)
|
|
0.20 0.20 clock uncertainty
|
|
0.00 0.20 clock reconvergence pessimism
|
|
-2.00 -1.80 output external delay
|
|
-1.80 data required time
|
|
---------------------------------------------------------
|
|
-1.80 data required time
|
|
-0.12 data arrival time
|
|
---------------------------------------------------------
|
|
1.92 slack (MET)
|
|
|
|
|
|
{"checks": [
|
|
{
|
|
"type": "check",
|
|
"path_group": "clk1",
|
|
"path_type": "min",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "reg2/D",
|
|
"source_clock": "clk1",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "clk1",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 7.798e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/A",
|
|
"net": "clk1",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/Z",
|
|
"net": "clk1_buf1",
|
|
"arrival": 2.420e-11,
|
|
"capacitance": 1.729e-15,
|
|
"slew": 8.079e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk1_buf1",
|
|
"arrival": 2.420e-11,
|
|
"slew": 8.079e-12
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 1.069e-10,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.316e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 1.069e-10,
|
|
"slew": 7.316e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "n4",
|
|
"arrival": 1.257e-10,
|
|
"capacitance": 1.140e-15,
|
|
"slew": 5.953e-12
|
|
},
|
|
{
|
|
"instance": "reg2",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg2/D",
|
|
"net": "n4",
|
|
"arrival": 1.257e-10,
|
|
"slew": 5.953e-12
|
|
}
|
|
],
|
|
"target_clock": "clk1",
|
|
"target_clock_edge": "rise",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "clk1",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 7.798e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/A",
|
|
"net": "clk1",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck1buf1",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf1/Z",
|
|
"net": "clk1_buf1",
|
|
"arrival": 2.675e-11,
|
|
"capacitance": 1.729e-15,
|
|
"slew": 8.079e-12
|
|
},
|
|
{
|
|
"instance": "ck1buf2",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf2/A",
|
|
"net": "clk1_buf1",
|
|
"arrival": 2.675e-11,
|
|
"slew": 8.079e-12
|
|
},
|
|
{
|
|
"instance": "ck1buf2",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck1buf2/Z",
|
|
"net": "clk1_buf2",
|
|
"arrival": 5.419e-11,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 6.565e-12
|
|
},
|
|
{
|
|
"instance": "reg2",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg2/CK",
|
|
"net": "clk1_buf2",
|
|
"arrival": 5.419e-11,
|
|
"slew": 6.565e-12
|
|
}
|
|
],
|
|
"data_arrival_time": 1.257e-10,
|
|
"crpr": -2.548e-12,
|
|
"margin": 6.736e-12,
|
|
"required_time": 3.584e-10,
|
|
"slack": -2.327e-10
|
|
},
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk2",
|
|
"path_type": "min",
|
|
"startpoint": "reg3/Q",
|
|
"endpoint": "out2",
|
|
"source_clock": "clk2",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "clk2",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 7.798e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck2buf",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck2buf/A",
|
|
"net": "clk2",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "ck2buf",
|
|
"cell": "CLKBUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "ck2buf/Z",
|
|
"net": "clk2_buf",
|
|
"arrival": 2.175e-11,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 6.551e-12
|
|
},
|
|
{
|
|
"instance": "reg3",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg3/CK",
|
|
"net": "clk2_buf",
|
|
"arrival": 2.175e-11,
|
|
"slew": 6.551e-12
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg3",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg3/Q",
|
|
"net": "n6",
|
|
"arrival": 9.773e-11,
|
|
"capacitance": 8.752e-16,
|
|
"slew": 5.625e-12
|
|
},
|
|
{
|
|
"instance": "buf4",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf4/A",
|
|
"net": "n6",
|
|
"arrival": 9.773e-11,
|
|
"slew": 5.625e-12
|
|
},
|
|
{
|
|
"instance": "buf4",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf4/Z",
|
|
"net": "out2",
|
|
"arrival": 1.180e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.903e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_crpr_data_checks",
|
|
"verilog_src": "",
|
|
"pin": "out2",
|
|
"arrival": 1.180e-10,
|
|
"slew": 3.903e-12
|
|
}
|
|
],
|
|
"target_clock": "clk2",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.180e-10,
|
|
"crpr": -0.000e+00,
|
|
"margin": -2.000e-09,
|
|
"required_time": -1.800e-09,
|
|
"slack": 1.918e-09
|
|
}
|
|
]
|
|
}
|
|
PASS: min formats with two clocks
|
|
--- report_checks between specific endpoints ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock source latency
|
|
0.00 10.00 ^ clk1 (in)
|
|
0.03 10.03 ^ ck1buf1/Z (CLKBUF_X1)
|
|
0.00 10.03 ^ reg1/CK (DFF_X1)
|
|
0.09 10.12 ^ reg1/Q (DFF_X1)
|
|
0.02 10.14 ^ buf2/Z (BUF_X1)
|
|
0.00 10.14 ^ reg2/D (DFF_X1)
|
|
10.14 data arrival time
|
|
|
|
5.00 5.00 clock clk1 (fall edge)
|
|
0.00 5.00 clock source latency
|
|
0.00 5.00 v clk1 (in)
|
|
0.02 5.02 v ck1buf1/Z (CLKBUF_X1)
|
|
0.00 5.02 v reg1/CK (DFF_X1)
|
|
-0.50 4.52 clock uncertainty
|
|
0.00 4.52 clock reconvergence pessimism
|
|
-0.10 4.42 data check setup time
|
|
4.42 data required time
|
|
---------------------------------------------------------
|
|
4.42 data required time
|
|
-10.14 data arrival time
|
|
---------------------------------------------------------
|
|
-5.72 slack (VIOLATED)
|
|
|
|
|
|
No paths found.
|
|
PASS: specific endpoint reports
|
|
--- report_checks with fields ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
|
|
Path Group: clk1
|
|
Path Type: max
|
|
|
|
Fanout Cap Slew Delay Time Description
|
|
-----------------------------------------------------------------------------
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
0.00 10.00 clock source latency
|
|
1 0.78 0.00 0.00 10.00 ^ clk1 (in)
|
|
clk1 (net)
|
|
0.00 0.00 10.00 ^ ck1buf1/A (CLKBUF_X1)
|
|
2 1.73 0.01 0.03 10.03 ^ ck1buf1/Z (CLKBUF_X1)
|
|
clk1_buf1 (net)
|
|
0.01 0.00 10.03 ^ reg1/CK (DFF_X1)
|
|
1 0.97 0.01 0.09 10.12 ^ reg1/Q (DFF_X1)
|
|
n3 (net)
|
|
0.01 0.00 10.12 ^ buf2/A (BUF_X1)
|
|
1 1.14 0.01 0.02 10.14 ^ buf2/Z (BUF_X1)
|
|
n4 (net)
|
|
0.01 0.00 10.14 ^ reg2/D (DFF_X1)
|
|
10.14 data arrival time
|
|
|
|
5.00 5.00 clock clk1 (fall edge)
|
|
0.00 5.00 clock source latency
|
|
1 0.70 0.00 0.00 5.00 v clk1 (in)
|
|
clk1 (net)
|
|
0.00 0.00 5.00 v ck1buf1/A (CLKBUF_X1)
|
|
2 1.56 0.01 0.02 5.02 v ck1buf1/Z (CLKBUF_X1)
|
|
clk1_buf1 (net)
|
|
0.01 0.00 5.02 v reg1/CK (DFF_X1)
|
|
-0.50 4.52 clock uncertainty
|
|
0.00 4.52 clock reconvergence pessimism
|
|
-0.10 4.42 data check setup time
|
|
4.42 data required time
|
|
-----------------------------------------------------------------------------
|
|
4.42 data required time
|
|
-10.14 data arrival time
|
|
-----------------------------------------------------------------------------
|
|
-5.72 slack (VIOLATED)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
Endpoint: out2 (output port clocked by clk2)
|
|
Path Group: clk2
|
|
Path Type: max
|
|
|
|
Fanout Cap Slew Delay Time Description
|
|
-----------------------------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.00 0.00 clock source latency
|
|
1 0.78 0.00 0.00 0.00 ^ clk2 (in)
|
|
clk2 (net)
|
|
0.00 0.00 0.00 ^ ck2buf/A (CLKBUF_X1)
|
|
1 0.95 0.01 0.02 0.02 ^ ck2buf/Z (CLKBUF_X1)
|
|
clk2_buf (net)
|
|
0.01 0.00 0.02 ^ reg3/CK (DFF_X1)
|
|
1 0.97 0.01 0.09 0.11 ^ reg3/Q (DFF_X1)
|
|
n6 (net)
|
|
0.01 0.00 0.11 ^ buf4/A (BUF_X1)
|
|
1 0.00 0.00 0.02 0.13 ^ buf4/Z (BUF_X1)
|
|
out2 (net)
|
|
0.00 0.00 0.13 ^ out2 (out)
|
|
0.13 data arrival time
|
|
|
|
8.00 8.00 clock clk2 (rise edge)
|
|
0.00 8.00 clock network delay (propagated)
|
|
-0.40 7.60 clock uncertainty
|
|
0.00 7.60 clock reconvergence pessimism
|
|
-2.00 5.60 output external delay
|
|
5.60 data required time
|
|
-----------------------------------------------------------------------------
|
|
5.60 data required time
|
|
-0.13 data arrival time
|
|
-----------------------------------------------------------------------------
|
|
5.47 slack (MET)
|
|
|
|
|
|
PASS: fields with full_clock_expanded
|
|
--- min_period checks with two clocks ---
|
|
clk1 period_min = 0.62 fmax = 1609.50
|
|
clk2 period_min = 0.00 fmax = inf
|
|
PASS: min_period with two clocks
|
|
--- pulse width checks ---
|
|
Required Actual
|
|
Pin Width Width Slack
|
|
------------------------------------------------------------
|
|
reg3/CK (high) 0.05 0.02 -0.04 (VIOLATED)
|
|
|
|
Pin: reg3/CK
|
|
Check: sequential_clock_pulse_width
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk2 (rise edge)
|
|
0.02 0.02 clock network delay (propagated)
|
|
0.00 0.02 reg3/CK
|
|
0.02 open edge arrival time
|
|
|
|
0.02 0.02 clock clk2 (fall edge)
|
|
0.02 0.04 clock network delay (propagated)
|
|
0.00 0.04 reg3/CK
|
|
0.00 0.04 clock reconvergence pessimism
|
|
0.04 close edge arrival time
|
|
---------------------------------------------------------
|
|
0.05 required pulse width (high)
|
|
0.02 actual pulse width
|
|
---------------------------------------------------------
|
|
-0.04 slack (VIOLATED)
|
|
|
|
|
|
Required Actual
|
|
Pin Width Width Slack
|
|
------------------------------------------------------------
|
|
reg3/CK (high) 0.05 0.02 -0.04 (VIOLATED)
|
|
reg3/CK (low) 0.05 0.02 -0.04 (VIOLATED)
|
|
reg2/CK (high) 0.05 0.02 -0.03 (VIOLATED)
|
|
reg2/CK (low) 0.05 0.02 -0.03 (VIOLATED)
|
|
reg1/CK (high) 0.05 0.02 -0.03 (VIOLATED)
|
|
reg1/CK (low) 0.05 0.02 -0.03 (VIOLATED)
|
|
|
|
PASS: pulse_width with two clocks
|
|
ALL PASSED
|