310 lines
8.4 KiB
Plaintext
310 lines
8.4 KiB
Plaintext
--- Corner commands ---
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Corner name: default
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Multi corner: 0
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PASS: corner commands
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--- ClkSkew report with propagated clock ---
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 setup skew
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 hold skew
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 setup skew
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 hold skew
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PASS: clock skew propagated
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--- ClkSkew with digits ---
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Clock clk
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0.025477 source latency reg1/CK ^
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-0.051608 target latency reg2/CK ^
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0.000000 CRPR
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--------------
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-0.026131 setup skew
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Clock clk
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0.025477 source latency reg1/CK ^
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-0.051608 target latency reg2/CK ^
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0.000000 CRPR
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--------------
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-0.026131 hold skew
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PASS: clock skew digits
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.03 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.03 0.05 latency
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0.03 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.02 0.05 latency
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0.03 skew
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.03 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.03 0.05 latency
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0.03 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.02 0.05 latency
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0.03 skew
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Clock clk
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rise -> rise
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min max
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0.000000 0.000000 source latency
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0.025477 network latency reg1/CK
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0.051608 network latency reg2/CK
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---------------
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0.025477 0.051608 latency
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0.026131 skew
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fall -> fall
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min max
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0.000000 0.000000 source latency
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0.024580 network latency reg1/CK
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0.050153 network latency reg2/CK
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---------------
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0.024580 0.050153 latency
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0.025572 skew
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PASS: clock latency
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--- worst_slack corner-specific ---
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Worst slack corner max: 7.864159989878772e-9
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Worst slack corner min: 7.392011308615665e-11
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PASS: worst_slack corner
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--- total_negative_slack corner ---
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TNS corner max: 0.0
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TNS corner min: 0.0
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PASS: tns corner
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--- worst_slack_vertex ---
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Worst vertex pin: out1
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PASS: worst_slack_vertex
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--- vertex_worst_arrival_path ---
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Worst arrival path pin: out1
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Worst arrival: 1.358400475437449e-10
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PASS: vertex_worst_arrival_path
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--- vertex_worst_slack_path ---
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Worst slack path pin: out1
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Worst slack: 7.864159989878772e-9
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PASS: vertex_worst_slack_path
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--- set_case_analysis and sim ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.05 0.05 clock network delay (propagated)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.08 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.86 slack (MET)
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Sim value and1/A2: 0
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in2 0 case=0
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PASS: case_analysis sim
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--- set_case_analysis 1 ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.05 0.05 clock network delay (propagated)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.08 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.86 slack (MET)
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Sim value and1/A1: 1
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PASS: case_analysis 1
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--- report with clock_uncertainty ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.08 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.30 9.70 clock uncertainty
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0.00 9.70 clock reconvergence pessimism
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-2.00 7.70 output external delay
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7.70 data required time
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---------------------------------------------------------
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7.70 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.56 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.00 0.03 ^ reg1/CK (DFF_X1)
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0.09 0.11 ^ reg1/Q (DFF_X1)
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0.02 0.13 ^ buf2/Z (BUF_X1)
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0.00 0.13 ^ reg2/D (DFF_X1)
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0.13 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.10 0.15 clock uncertainty
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0.00 0.15 clock reconvergence pessimism
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0.01 0.16 library hold time
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0.16 data required time
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---------------------------------------------------------
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0.16 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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-0.03 slack (VIOLATED)
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.30 clock uncertainty
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0.00 CRPR
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--------------
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0.27 setup skew
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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-0.10 clock uncertainty
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0.00 CRPR
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--------------
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-0.13 hold skew
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PASS: clock uncertainty
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--- report with set_inter_clock_uncertainty ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.08 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.15 9.85 inter-clock uncertainty
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0.00 9.85 clock reconvergence pessimism
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-2.00 7.85 output external delay
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7.85 data required time
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---------------------------------------------------------
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7.85 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.71 slack (MET)
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PASS: inter_clock_uncertainty
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--- find_clk_min_period ---
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Min period: 1.1478817896204419e-10
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Min period (with port paths): 2.1358399493465186e-9
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PASS: find_clk_min_period
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ALL PASSED
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