407 lines
11 KiB
Plaintext
407 lines
11 KiB
Plaintext
--- report_clock_skew -setup ---
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Clock clk
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0.05 source latency reg1/CK ^
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-0.08 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 setup skew
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PASS: clock_skew setup
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--- report_clock_skew -hold ---
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Clock clk
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0.05 source latency reg1/CK ^
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-0.08 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 hold skew
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PASS: clock_skew hold
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--- report_clock_skew -clock clk ---
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Clock clk
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0.05 source latency reg1/CK ^
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-0.08 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 setup skew
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PASS: clock_skew named
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--- report_clock_skew -digits 6 ---
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Clock clk
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0.051447 source latency reg1/CK ^
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-0.079237 target latency reg2/CK ^
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0.000000 CRPR
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--------------
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-0.027789 setup skew
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PASS: clock_skew digits
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--- report_clock_skew -include_internal_latency setup ---
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Clock clk
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0.05 source latency reg1/CK ^
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-0.08 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 setup skew
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PASS: clock_skew internal_latency setup
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--- report_clock_skew -include_internal_latency hold ---
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Clock clk
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0.05 source latency reg1/CK ^
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-0.08 target latency reg2/CK ^
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0.00 CRPR
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--------------
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-0.03 hold skew
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PASS: clock_skew internal_latency hold
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--- report_clock_skew -digits 6 -include_internal_latency ---
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Clock clk
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0.051447 source latency reg1/CK ^
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-0.079237 target latency reg2/CK ^
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0.000000 CRPR
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--------------
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-0.027789 setup skew
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PASS: clock_skew digits + internal
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--- clock_latency + uncertainty ---
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Clock clk
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0.35 source latency reg1/CK ^
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-0.38 target latency reg2/CK ^
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0.20 clock uncertainty
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0.00 CRPR
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--------------
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0.17 setup skew
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Clock clk
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0.35 source latency reg1/CK ^
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-0.38 target latency reg2/CK ^
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-0.10 clock uncertainty
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0.00 CRPR
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--------------
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-0.13 hold skew
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Clock clk
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0.3514 source latency reg1/CK ^
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-0.3792 target latency reg2/CK ^
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0.2000 clock uncertainty
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0.0000 CRPR
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--------------
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0.1722 setup skew
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PASS: latency + uncertainty skew
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.30 0.30 source latency
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0.35 network latency reg1/CK
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0.38 network latency reg2/CK
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---------------
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0.65 0.68 latency
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0.03 skew
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fall -> fall
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min max
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0.30 0.30 source latency
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0.36 network latency reg1/CK
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0.38 network latency reg2/CK
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---------------
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0.66 0.68 latency
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0.03 skew
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PASS: clock_latency
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--- report_clock_latency -include_internal_latency ---
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Clock clk
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rise -> rise
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min max
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0.30 0.30 source latency
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0.35 network latency reg1/CK
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0.38 network latency reg2/CK
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---------------
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0.65 0.68 latency
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0.03 skew
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fall -> fall
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min max
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0.30 0.30 source latency
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0.36 network latency reg1/CK
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0.38 network latency reg2/CK
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---------------
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0.66 0.68 latency
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0.03 skew
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PASS: clock_latency internal
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--- report_clock_latency -clock clk ---
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Clock clk
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rise -> rise
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min max
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0.30 0.30 source latency
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0.35 network latency reg1/CK
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0.38 network latency reg2/CK
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---------------
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0.65 0.68 latency
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0.03 skew
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fall -> fall
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min max
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0.30 0.30 source latency
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0.36 network latency reg1/CK
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0.38 network latency reg2/CK
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---------------
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0.66 0.68 latency
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0.03 skew
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PASS: clock_latency named
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--- report_clock_latency -digits 6 ---
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Clock clk
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rise -> rise
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min max
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0.300000 0.300000 source latency
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0.351447 network latency reg1/CK
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0.379237 network latency reg2/CK
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---------------
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0.651447 0.679237 latency
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0.027789 skew
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fall -> fall
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min max
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0.300000 0.300000 source latency
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0.355433 network latency reg1/CK
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0.382804 network latency reg2/CK
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---------------
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0.655433 0.682804 latency
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0.027370 skew
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PASS: clock_latency digits
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--- report_clock_min_period ---
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clk period_min = 0.31 fmax = 3177.18
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PASS: clock_min_period
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--- report_clock_min_period -clocks clk ---
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clk period_min = 0.31 fmax = 3177.18
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PASS: clock_min_period named
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--- report_clock_min_period -include_port_paths ---
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clk period_min = 1.36 fmax = 733.42
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PASS: clock_min_period port_paths
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--- find_clk_min_period ---
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clk min_period: 3.147446747675531e-10
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clk min_period (port): 1.3634764428616108e-9
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PASS: find_clk_min_period
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--- add multicycle ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.38 0.38 clock network delay (propagated)
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0.00 0.38 ^ reg2/CK (DFF_X1)
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0.08 0.46 ^ reg2/Q (DFF_X1)
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0.00 0.46 ^ out1 (out)
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0.46 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.30 20.30 clock network delay (propagated)
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-0.20 20.10 clock uncertainty
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0.00 20.10 clock reconvergence pessimism
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-1.00 19.10 output external delay
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19.10 data required time
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---------------------------------------------------------
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19.10 data required time
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-0.46 data arrival time
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---------------------------------------------------------
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18.64 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.35 0.35 clock network delay (propagated)
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0.00 0.35 ^ reg1/CK (DFF_X1)
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0.09 0.44 ^ reg1/Q (DFF_X1)
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0.02 0.46 ^ buf2/Z (BUF_X1)
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0.00 0.46 ^ reg2/D (DFF_X1)
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0.46 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.38 0.38 clock network delay (propagated)
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0.10 0.48 clock uncertainty
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0.00 0.48 clock reconvergence pessimism
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0.48 ^ reg2/CK (DFF_X1)
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0.01 0.49 library hold time
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0.49 data required time
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---------------------------------------------------------
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0.49 data required time
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-0.46 data arrival time
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---------------------------------------------------------
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-0.03 slack (VIOLATED)
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PASS: multicycle
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--- skew after multicycle ---
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Clock clk
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0.35 source latency reg1/CK ^
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-0.38 target latency reg2/CK ^
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0.20 clock uncertainty
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0.00 CRPR
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--------------
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0.17 setup skew
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Clock clk
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0.35 source latency reg1/CK ^
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-0.38 target latency reg2/CK ^
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-0.10 clock uncertainty
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0.00 CRPR
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--------------
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-0.13 hold skew
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PASS: skew after multicycle
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--- set_clock_transition ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.30 0.30 clock source latency
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0.00 0.30 ^ clk (in)
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0.05 0.35 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.38 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.38 ^ reg2/CK (DFF_X1)
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0.08 0.46 ^ reg2/Q (DFF_X1)
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0.00 0.46 ^ out1 (out)
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0.46 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.30 20.30 clock network delay (propagated)
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-0.20 20.10 clock uncertainty
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0.00 20.10 clock reconvergence pessimism
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-1.00 19.10 output external delay
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19.10 data required time
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---------------------------------------------------------
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19.10 data required time
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-0.46 data arrival time
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---------------------------------------------------------
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18.64 slack (MET)
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PASS: clock transitions
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--- report_checks -format full_clock ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.30 0.30 clock source latency
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0.00 0.30 ^ clk (in)
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0.05 0.35 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.38 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.38 ^ reg2/CK (DFF_X1)
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0.08 0.46 ^ reg2/Q (DFF_X1)
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0.00 0.46 ^ out1 (out)
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0.46 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.30 20.30 clock network delay (propagated)
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-0.20 20.10 clock uncertainty
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0.00 20.10 clock reconvergence pessimism
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-1.00 19.10 output external delay
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19.10 data required time
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---------------------------------------------------------
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19.10 data required time
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-0.46 data arrival time
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---------------------------------------------------------
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18.64 slack (MET)
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PASS: full_clock
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--- report_checks -format full_clock_expanded ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.30 0.30 clock source latency
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0.00 0.30 ^ clk (in)
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0.05 0.35 ^ ckbuf1/Z (CLKBUF_X1)
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0.00 0.35 ^ reg1/CK (DFF_X1)
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0.09 0.44 ^ reg1/Q (DFF_X1)
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0.02 0.46 ^ buf2/Z (BUF_X1)
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0.00 0.46 ^ reg2/D (DFF_X1)
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0.46 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.30 0.30 clock source latency
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0.00 0.30 ^ clk (in)
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0.05 0.35 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.38 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.38 ^ reg2/CK (DFF_X1)
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0.10 0.48 clock uncertainty
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0.00 0.48 clock reconvergence pessimism
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0.01 0.49 library hold time
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0.49 data required time
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---------------------------------------------------------
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0.49 data required time
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-0.46 data arrival time
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---------------------------------------------------------
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-0.03 slack (VIOLATED)
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PASS: full_clock_expanded min
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--- inter-clock uncertainty ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.30 0.30 clock source latency
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0.00 0.30 ^ clk (in)
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0.05 0.35 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.38 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.38 ^ reg2/CK (DFF_X1)
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0.08 0.46 ^ reg2/Q (DFF_X1)
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0.00 0.46 ^ out1 (out)
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0.46 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.30 20.30 clock network delay (propagated)
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-0.15 20.15 inter-clock uncertainty
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0.00 20.15 clock reconvergence pessimism
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-1.00 19.15 output external delay
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19.15 data required time
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---------------------------------------------------------
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19.15 data required time
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-0.46 data arrival time
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---------------------------------------------------------
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18.69 slack (MET)
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PASS: inter_clock_uncertainty
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--- report_pulse_width_checks ---
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PASS: pulse_width_checks
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--- report_pulse_width_checks -verbose ---
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PASS: pulse_width_checks verbose
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--- report_clock_min_period after multicycle ---
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clk period_min = 0.00 fmax = inf
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PASS: clock_min_period after multicycle
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ALL PASSED
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