146 lines
4.7 KiB
Tcl
146 lines
4.7 KiB
Tcl
# Test CheckTiming.cc, GatedClk.cc, and various check commands
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_check_timing.v
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link_design search_check_timing
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create_clock -name clk -period 10 [get_ports clk]
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create_clock -name clk2 -period 15 [get_ports clk2]
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# Intentionally leave some ports without delays for check_setup testing
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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# in3 and in_unconst deliberately have no input delay
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk2 2.0 [get_ports out2]
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# out_unconst deliberately has no output delay
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puts "--- check_setup all flags ---"
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check_setup -verbose
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puts "PASS: check_setup verbose"
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puts "--- check_setup -no_input_delay ---"
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check_setup -verbose -no_input_delay
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puts "PASS: check_setup no_input_delay"
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puts "--- check_setup -no_output_delay ---"
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check_setup -verbose -no_output_delay
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puts "PASS: check_setup no_output_delay"
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puts "--- check_setup -no_clock ---"
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check_setup -verbose -no_clock
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puts "PASS: check_setup no_clock"
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puts "--- check_setup -unconstrained_endpoints ---"
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check_setup -verbose -unconstrained_endpoints
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puts "PASS: check_setup unconstrained_endpoints"
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puts "--- check_setup -loops ---"
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check_setup -verbose -loops
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puts "PASS: check_setup loops"
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puts "--- check_setup -generated_clocks ---"
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check_setup -verbose -generated_clocks
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puts "PASS: check_setup generated_clocks"
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puts "--- check_setup multiple flags combined ---"
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check_setup -verbose -no_input_delay -no_output_delay -unconstrained_endpoints -loops -generated_clocks
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puts "PASS: check_setup combined flags"
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puts "--- report_check_types all ---"
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report_check_types -verbose
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puts "PASS: report_check_types verbose"
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puts "--- report_check_types individual ---"
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report_check_types -max_delay
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report_check_types -min_delay
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report_check_types -max_slew
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report_check_types -max_fanout
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report_check_types -max_capacitance
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report_check_types -min_pulse_width
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report_check_types -min_period
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report_check_types -max_skew
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report_check_types -violators
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puts "PASS: report_check_types individual"
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puts "--- set_max_transition and check ---"
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set_max_transition 0.5 [current_design]
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report_check_types -max_slew -verbose
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puts "PASS: set_max_transition check"
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puts "--- set_max_capacitance and check ---"
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set_max_capacitance 0.05 [current_design]
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report_check_types -max_capacitance -verbose
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puts "PASS: set_max_capacitance check"
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puts "--- set_max_fanout and check ---"
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set_max_fanout 10 [current_design]
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report_check_types -max_fanout -verbose
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puts "PASS: set_max_fanout check"
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puts "--- report_checks with unconstrained ---"
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report_checks -unconstrained -path_delay max
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puts "PASS: report_checks unconstrained"
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puts "--- set_clock_groups and check ---"
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set_clock_groups -name cg1 -asynchronous -group {clk} -group {clk2}
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report_checks -path_delay max
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check_setup -verbose
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unset_clock_groups -asynchronous -name cg1
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puts "PASS: clock_groups check"
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puts "--- report_clock_min_period ---"
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report_clock_min_period
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report_clock_min_period -include_port_paths
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report_clock_min_period -clocks clk
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report_clock_min_period -clocks clk2
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puts "PASS: clock_min_period"
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puts "--- Gated clock enable settings ---"
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sta::set_propagate_gated_clock_enable 1
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puts "gated_clk_enable: [sta::propagate_gated_clock_enable]"
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report_checks -path_delay max
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sta::set_propagate_gated_clock_enable 0
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puts "PASS: gated clock enable settings"
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puts "--- Gated clock check settings ---"
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sta::set_gated_clk_checks_enabled 1
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puts "gated_clk_checks: [sta::gated_clk_checks_enabled]"
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report_checks -path_delay max
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sta::set_gated_clk_checks_enabled 0
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puts "PASS: gated clock checks"
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puts "--- Recovery/removal checks ---"
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sta::set_recovery_removal_checks_enabled 1
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puts "recovery_removal: [sta::recovery_removal_checks_enabled]"
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report_checks -path_delay max
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sta::set_recovery_removal_checks_enabled 0
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puts "PASS: recovery/removal settings"
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puts "--- Various STA variable settings ---"
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sta::set_preset_clr_arcs_enabled 1
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puts "preset_clr: [sta::preset_clr_arcs_enabled]"
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sta::set_preset_clr_arcs_enabled 0
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sta::set_cond_default_arcs_enabled 1
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puts "cond_default: [sta::cond_default_arcs_enabled]"
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sta::set_cond_default_arcs_enabled 0
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sta::set_bidirect_inst_paths_enabled 1
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puts "bidirect_inst: [sta::bidirect_inst_paths_enabled]"
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sta::set_bidirect_inst_paths_enabled 0
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sta::set_bidirect_net_paths_enabled 1
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puts "bidirect_net: [sta::bidirect_net_paths_enabled]"
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sta::set_bidirect_net_paths_enabled 0
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sta::set_dynamic_loop_breaking 1
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puts "dynamic_loop: [sta::dynamic_loop_breaking]"
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sta::set_dynamic_loop_breaking 0
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sta::set_use_default_arrival_clock 1
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puts "default_arrival_clk: [sta::use_default_arrival_clock]"
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sta::set_use_default_arrival_clock 0
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puts "PASS: variable settings"
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puts "ALL PASSED"
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