391 lines
14 KiB
Plaintext
391 lines
14 KiB
Plaintext
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
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--- Reading SPEF ---
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PASS: read_spef completed
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--- Parasitic annotation ---
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Found 0 unannotated drivers.
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Found 0 partially unannotated drivers.
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PASS: report_parasitic_annotation
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Found 0 unannotated drivers.
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Found 0 partially unannotated drivers.
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PASS: report_parasitic_annotation -report_unannotated
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--- Annotated delay reporting ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 4 0 4
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----------------------------------------------------------------
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10 0 10
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PASS: report_annotated_delay -cell -net
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 5 0 5
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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6 0 6
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PASS: report_annotated_delay -from_in_ports -to_out_ports
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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----------------------------------------------------------------
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6 0 6
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PASS: report_annotated_delay -cell
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 4 0 4
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----------------------------------------------------------------
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4 0 4
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PASS: report_annotated_delay -net
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 4 0 4
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net arcs from primary inputs 5 0 5
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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16 0 16
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Annotated Arcs
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PASS: report_annotated_delay -report_annotated
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 4 0 4
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net arcs from primary inputs 5 0 5
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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16 0 16
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Unannotated Arcs
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primary input net clk1 -> r1/CLK
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primary input net clk2 -> r2/CLK
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primary input net clk3 -> r3/CLK
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primary input net in1 -> r1/D
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primary input net in2 -> r2/D
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delay r1/CLK -> r1/Q
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internal net r1/Q -> u2/A
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delay r2/CLK -> r2/Q
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internal net r2/Q -> u1/A
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delay r3/CLK -> r3/Q
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primary output net r3/Q -> out
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delay u1/A -> u1/Y
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internal net u1/Y -> u2/B
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delay u2/A -> u2/Y
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delay u2/B -> u2/Y
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internal net u2/Y -> r3/D
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PASS: report_annotated_delay -report_unannotated
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--- Timing with parasitics ---
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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12.11 12.11 clock network delay (propagated)
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0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
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61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
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15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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201.72 data arrival time
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500.00 500.00 clock clk (rise edge)
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11.92 511.92 clock network delay (propagated)
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0.00 511.92 clock reconvergence pessimism
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511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-8.46 503.46 library setup time
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503.46 data required time
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---------------------------------------------------------
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503.46 data required time
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-201.72 data arrival time
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---------------------------------------------------------
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301.74 slack (MET)
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PASS: report_checks with parasitics
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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12.16 13.16 v r1/D (DFFHQx4_ASAP7_75t_R)
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13.16 data arrival time
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0.00 0.00 clock clk (rise edge)
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12.11 12.11 clock network delay (propagated)
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0.00 12.11 clock reconvergence pessimism
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12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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12.51 24.61 library hold time
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24.61 data required time
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---------------------------------------------------------
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24.61 data required time
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-13.16 data arrival time
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---------------------------------------------------------
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-11.46 slack (VIOLATED)
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PASS: report_checks min path
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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12.11 12.11 clock network delay (propagated)
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0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
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61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
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15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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201.72 data arrival time
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500.00 500.00 clock clk (rise edge)
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11.92 511.92 clock network delay (propagated)
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0.00 511.92 clock reconvergence pessimism
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511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-8.46 503.46 library setup time
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503.46 data required time
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---------------------------------------------------------
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503.46 data required time
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-201.72 data arrival time
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---------------------------------------------------------
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301.74 slack (MET)
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PASS: report_checks max path
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Slew Delay Time Description
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-----------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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14.02 10.00 0.00 1.00 ^ in1 (in)
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48.93 12.28 13.28 ^ r1/D (DFFHQx4_ASAP7_75t_R)
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13.28 data arrival time
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0.00 500.00 500.00 clock clk (rise edge)
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11.92 511.92 clock network delay (propagated)
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0.00 511.92 clock reconvergence pessimism
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511.92 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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-6.94 504.98 library setup time
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504.98 data required time
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-----------------------------------------------------------------------
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504.98 data required time
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-13.28 data arrival time
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-----------------------------------------------------------------------
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491.70 slack (MET)
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PASS: report_checks from in1 with fields
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Startpoint: in2 (input port clocked by clk)
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Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Slew Delay Time Description
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-----------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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14.02 10.00 0.00 1.00 ^ in2 (in)
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48.93 12.28 13.28 ^ r2/D (DFFHQx4_ASAP7_75t_R)
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13.28 data arrival time
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0.00 500.00 500.00 clock clk (rise edge)
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11.92 511.92 clock network delay (propagated)
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0.00 511.92 clock reconvergence pessimism
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511.92 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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-6.94 504.98 library setup time
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504.98 data required time
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-----------------------------------------------------------------------
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504.98 data required time
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-13.28 data arrival time
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-----------------------------------------------------------------------
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491.70 slack (MET)
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PASS: report_checks from in2 with fields
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--- report_net ---
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Net r1q
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Pin capacitance: 0.40-0.52
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Wire capacitance: 13.40-13.40
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Total capacitance: 13.80-13.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r1/Q output (DFFHQx4_ASAP7_75t_R)
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Load pins
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u2/A input (AND2x2_ASAP7_75t_R) 0.40-0.52
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PASS: report_net r1q
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Net r2q
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Pin capacitance: 0.44-0.58
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Wire capacitance: 13.40-13.40
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Total capacitance: 13.84-13.98
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r2/Q output (DFFHQx4_ASAP7_75t_R)
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Load pins
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u1/A input (BUFx2_ASAP7_75t_R) 0.44-0.58
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PASS: report_net r2q
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Net u1z
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Pin capacitance: 0.32-0.57
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Wire capacitance: 13.40-13.40
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Total capacitance: 13.72-13.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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u1/Y output (BUFx2_ASAP7_75t_R)
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Load pins
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u2/B input (AND2x2_ASAP7_75t_R) 0.32-0.57
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PASS: report_net u1z
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Net u2z
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Pin capacitance: 0.55-0.62
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Wire capacitance: 13.40-13.40
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Total capacitance: 13.95-14.02
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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u2/Y output (AND2x2_ASAP7_75t_R)
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Load pins
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r3/D input (DFFHQx4_ASAP7_75t_R) 0.55-0.62
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PASS: report_net u2z
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Net out
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Pin capacitance: 0.00
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Wire capacitance: 13.40
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Total capacitance: 13.40
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r3/Q output (DFFHQx4_ASAP7_75t_R)
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Load pins
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out output port
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PASS: report_net out
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Net in1
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Pin capacitance: 0.55-0.62
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Wire capacitance: 13.40-13.40
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Total capacitance: 13.95-14.02
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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in1 input port
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Load pins
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r1/D input (DFFHQx4_ASAP7_75t_R) 0.55-0.62
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PASS: report_net in1
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Net r1q
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Pin capacitance: 0.399352-0.522565
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Wire capacitance: 13.399999-13.400000
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Total capacitance: 13.799351-13.922565
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r1/Q output (DFFHQx4_ASAP7_75t_R)
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Load pins
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u2/A input (AND2x2_ASAP7_75t_R) 0.399352-0.522565
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PASS: report_net -digits 6
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--- Manual parasitic models ---
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PASS: set_pi_model
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PASS: set_elmore
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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12.11 12.11 clock network delay (propagated)
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0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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34.88 110.50 ^ u1/Y (BUFx2_ASAP7_75t_R)
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32.94 143.44 ^ u2/Y (AND2x2_ASAP7_75t_R)
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15.75 159.19 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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159.19 data arrival time
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500.00 500.00 clock clk (rise edge)
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11.92 511.92 clock network delay (propagated)
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0.00 511.92 clock reconvergence pessimism
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511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-8.43 503.49 library setup time
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503.49 data required time
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---------------------------------------------------------
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503.49 data required time
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-159.19 data arrival time
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---------------------------------------------------------
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344.30 slack (MET)
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PASS: report_checks after manual parasitics
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ALL PASSED
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