552 lines
18 KiB
Plaintext
552 lines
18 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: initial setup
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--- pattern matching ---
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cells *: 3
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cells ???1: 3
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cells b*: 1
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cells buf*: 1
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cells and*: 1
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cells reg*: 1
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Warning: network_escaped_names.tcl line 1, instance 'nonexistent_*' not found.
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cells nonexistent_*: 0
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PASS: pattern matching
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--- pin pattern matching ---
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buf1/* pins: 2
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*/A pins: 1
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*/Z pins: 1
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*/ZN pins: 1
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*/CK pins: 1
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hier pins: 11
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*/*1 pins: 1
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PASS: pin pattern matching
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--- net pattern matching ---
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all nets: 6
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n* nets: 2
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hier nets: 6
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PASS: net pattern matching
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--- port pattern matching ---
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all ports: 4
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in* ports: 2
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out* ports: 1
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clk* ports: 1
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?n? ports: 2
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PASS: port pattern matching
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--- lib cell pattern matching ---
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all lib cells: 134
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INV* lib cells: 6
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BUF* lib cells: 6
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NAND* lib cells: 9
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*/* lib cells: 134
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*/INV* lib cells: 6
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*/DFF* lib cells: 8
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*/AOI* lib cells: 15
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*/OAI* lib cells: 16
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*/MUX* lib cells: 2
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*/SDFF* lib cells: 8
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*/FILL* lib cells: 6
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*/CLKGATE* lib cells: 8
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*/TLAT* lib cells: 1
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*/TINV* lib cells: 1
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PASS: lib cell pattern matching
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--- lib pin pattern matching ---
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INV_X1/* lib pins: 2
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BUF_X1/* lib pins: 2
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DFF_X1/* lib pins: 6
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NAND2_X1/* lib pins: 3
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AOI21_X1/* lib pins: 4
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SDFF_X1/* lib pins: 8
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CLKGATETST_X1/* lib pins: 5
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FA_X1/* lib pins: 5
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PASS: lib pin pattern matching
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--- current_design ---
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current_design: network_test1
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--- timing reports ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in2 (in)
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0.04 0.04 ^ and1/ZN (AND2_X1)
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0.00 0.04 ^ reg1/D (DFF_X1)
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0.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.04 data arrival time
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---------------------------------------------------------
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0.04 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.06 0.06 v and1/ZN (AND2_X1)
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0.00 0.06 v reg1/D (DFF_X1)
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0.06 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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9.90 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in1 (in)
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0.03 0.03 ^ buf1/Z (BUF_X1)
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0.03 0.06 ^ and1/ZN (AND2_X1)
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0.00 0.06 ^ reg1/D (DFF_X1)
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0.06 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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9.91 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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PASS: timing reports
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Warning: network_escaped_names.tcl line 1, unknown field nets.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.10 0.00 0.00 v in1 (in)
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0.10 0.00 0.00 v buf1/A (BUF_X1)
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1 0.87 0.01 0.06 0.06 v buf1/Z (BUF_X1)
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0.01 0.00 0.06 v and1/A1 (AND2_X1)
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1 1.06 0.01 0.03 0.08 v and1/ZN (AND2_X1)
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0.01 0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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-----------------------------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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-----------------------------------------------------------------
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0.000000 0.000000 clock clk (rise edge)
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0.000000 0.000000 clock network delay (ideal)
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0.000000 0.000000 v input external delay
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0.000000 0.000000 v in1 (in)
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0.056245 0.056245 v buf1/Z (BUF_X1)
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0.026951 0.083196 v and1/ZN (AND2_X1)
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0.000000 0.083196 v reg1/D (DFF_X1)
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0.083196 data arrival time
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10.000000 10.000000 clock clk (rise edge)
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0.000000 10.000000 clock network delay (ideal)
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0.000000 10.000000 clock reconvergence pessimism
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10.000000 ^ reg1/CK (DFF_X1)
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-0.040412 9.959588 library setup time
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9.959588 data required time
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-----------------------------------------------------------------
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9.959588 data required time
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-0.083196 data arrival time
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-----------------------------------------------------------------
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9.876392 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
9.88 slack (MET)
|
|
|
|
|
|
PASS: report formats
|
|
Group Slack
|
|
--------------------------------------------
|
|
clk 0.04
|
|
clk 9.88
|
|
|
|
max slew
|
|
|
|
Pin Limit Slew Slack
|
|
------------------------------------------------------------
|
|
reg1/QN 0.20 0.01 0.19 (MET)
|
|
|
|
max capacitance
|
|
|
|
Pin Limit Cap Slack
|
|
------------------------------------------------------------
|
|
and1/ZN 60.58 1.14 59.44 (MET)
|
|
|
|
PASS: report_check_types
|
|
Group Internal Switching Leakage Total
|
|
Power Power Power Power (Watts)
|
|
----------------------------------------------------------------
|
|
Sequential 5.41e-07 0.00e+00 7.88e-08 6.20e-07 84.3%
|
|
Combinational 5.67e-08 1.25e-08 4.65e-08 1.16e-07 15.7%
|
|
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
|
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
|
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
|
----------------------------------------------------------------
|
|
Total 5.97e-07 1.25e-08 1.25e-07 7.35e-07 100.0%
|
|
81.3% 1.7% 17.0%
|
|
PASS: report_power
|
|
ALL PASSED
|