148 lines
5.2 KiB
Plaintext
148 lines
5.2 KiB
Plaintext
PASS: read Sky130 library
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sdfxtp_1 area = 26.275200
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PASS: sdfxtp_1 has test_cell
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sdfxtp_1/SCD dir=input
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sdfxtp_1/SCE dir=input
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sdfxtp_1/CLK dir=input
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sdfxtp_1/D dir=input
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sdfxtp_1/Q dir=output
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PASS: scan cell port queries
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sdfxbp_1 area = 30.028799
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PASS: second scan cell
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sky130_fd_sc_hd__ebufn_1 area = 10.009600
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sky130_fd_sc_hd__ebufn_1 Z tristate_enable = !TE_B
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sky130_fd_sc_hd__ebufn_2 area = 11.260800
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sky130_fd_sc_hd__ebufn_2 Z tristate_enable = !TE_B
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sky130_fd_sc_hd__ebufn_4 area = 16.265600
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sky130_fd_sc_hd__ebufn_4 Z tristate_enable = !TE_B
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sky130_fd_sc_hd__ebufn_8 area = 26.275200
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sky130_fd_sc_hd__ebufn_8 Z tristate_enable = !TE_B
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PASS: tristate cell queries
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sky130_fd_sc_hd__dlxtp_1 area = 15.014400
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sky130_fd_sc_hd__dlxtn_1 area = 15.014400
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sky130_fd_sc_hd__dlxbn_1 area = 18.768000
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sky130_fd_sc_hd__dlxbp_1 area = 18.768000
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PASS: latch cell queries
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sky130_fd_sc_hd__dfrtp_1 area=25.024000 is_buf=0 is_inv=0
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sky130_fd_sc_hd__dfstp_1 area=26.275200 is_buf=0 is_inv=0
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sky130_fd_sc_hd__dfxtp_1 area=20.019199 is_buf=0 is_inv=0
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sky130_fd_sc_hd__dfbbp_1 area=32.531200 is_buf=0 is_inv=0
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PASS: DFF with async set/clear
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PASS: internal power queries
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sky130_fd_sc_hd__and2_1/X dir=output func=A*B
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sky130_fd_sc_hd__or2_1/X dir=output func=A+B
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sky130_fd_sc_hd__xor2_1/X dir=output func=(A*!B)+(!A*B)
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sky130_fd_sc_hd__xnor2_1/Y dir=output func=(!A*!B)+(A*B)
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sky130_fd_sc_hd__mux2_1/X dir=output func=(A0*!S)+(A1*S)
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PASS: port function queries
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PASS: read Nangate45
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INV_X1/A cap=0.001700
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INV_X2/A cap=0.003251
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INV_X4/A cap=0.006258
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BUF_X1/A cap=0.000975
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BUF_X2/A cap=0.001779
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BUF_X4/A cap=0.003402
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NAND2_X1/A1 cap=0.001599
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NAND2_X1/A2 cap=0.001664
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NOR2_X1/A1 cap=0.001714
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NOR2_X1/A2 cap=0.001651
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AOI21_X1/A cap=0.001626
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AOI21_X1/B1 cap=0.001647
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AOI21_X1/B2 cap=0.001677
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OAI21_X1/A cap=0.001671
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OAI21_X1/B1 cap=0.001662
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OAI21_X1/B2 cap=0.001572
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PASS: port capacitance queries
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DFF_X1 arc_sets = 5
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DFFR_X1 arc_sets = 16
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DFFS_X1 arc_sets = 16
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DFFRS_X1 arc_sets = 35
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PASS: timing arc queries
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PASS: read fakeram library (bus ports)
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fakeram/clk dir=input bus=0 bundle=0 has_members=0
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fakeram/rd_out dir=output bus=1 bundle=0 has_members=1
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member_count = 7
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fakeram/we_in dir=input bus=0 bundle=0 has_members=0
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fakeram/ce_in dir=input bus=0 bundle=0 has_members=0
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fakeram/addr_in dir=input bus=1 bundle=0 has_members=1
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member_count = 6
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fakeram/wd_in dir=input bus=1 bundle=0 has_members=1
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member_count = 7
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fakeram/w_mask_in dir=input bus=1 bundle=0 has_members=1
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member_count = 7
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PASS: bus port queries
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PASS: read ASAP7 SEQ (latch + statetable)
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DLLx1 arc_sets = 6
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PASS: ASAP7 latch cell arcs
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ICGx1 arc_sets = 13
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PASS: ASAP7 ICG cell arcs
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PASS: design setup
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: report_checks
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Group Internal Switching Leakage Total
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Power Power Power Power (Watts)
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----------------------------------------------------------------
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Sequential 1.52e-06 6.90e-09 2.36e-07 1.76e-06 84.7%
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Combinational 1.22e-07 7.11e-08 1.25e-07 3.18e-07 15.3%
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Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
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Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
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Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
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----------------------------------------------------------------
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Total 1.64e-06 7.80e-08 3.61e-07 2.08e-06 100.0%
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78.9% 3.8% 17.4%
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PASS: report_power
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PASS: write_liberty
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ALL PASSED
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