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OpenSTA
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OpenSTA/verilog
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Jaehyun Kim 1b97c9c9b4 Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenSTA into secure-sta-test-by-opus 2026-02-27 11:56:33 +09:00
..
test test: Add `save_ok` script 2026-02-27 11:12:27 +09:00
Verilog.i rel 3.0 2026-01-13 09:36:45 -07:00
Verilog.tcl rel 3.0 2026-01-13 09:36:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReader.cc rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReaderPvt.hh rel 3.0 2026-01-13 09:36:45 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc fix merge 2026-02-25 19:48:36 +00:00