81 lines
2.8 KiB
Plaintext
81 lines
2.8 KiB
Plaintext
Warning 415: sdc_write_comprehensive.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
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Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: group_clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.60 0.60 clock network delay (propagated)
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0.00 0.60 ^ reg2/CK (DFF_X1)
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0.09 0.69 ^ reg2/Q (DFF_X1)
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0.00 0.69 ^ out1 (out)
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0.69 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.50 10.50 clock network delay (propagated)
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-0.20 10.30 clock uncertainty
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0.00 10.30 clock reconvergence pessimism
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-3.00 7.30 output external delay
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7.30 data required time
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---------------------------------------------------------
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7.30 data required time
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-0.69 data arrival time
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---------------------------------------------------------
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6.61 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_fast)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk1_fast (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 ^ reg2/CK (DFF_X1)
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0.09 5.09 ^ reg2/Q (DFF_X1)
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0.00 5.09 ^ out1 (out)
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5.09 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.50 10.50 clock network delay (propagated)
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-0.20 10.30 clock uncertainty
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0.00 10.30 clock reconvergence pessimism
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-3.00 7.30 output external delay
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7.30 data required time
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---------------------------------------------------------
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7.30 data required time
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-5.09 data arrival time
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---------------------------------------------------------
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2.21 slack (MET)
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Startpoint: reg3/Q (clock source 'gen_mul3')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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13.33 13.33 clock gen_mul3 (rise edge)
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0.00 13.33 clock network delay
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13.33 ^ out2 (out)
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13.33 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-13.33 data arrival time
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---------------------------------------------------------
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3.37 slack (MET)
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