287 lines
9.6 KiB
Tcl
287 lines
9.6 KiB
Tcl
# Test SDC network querying and bus range operations for coverage improvement.
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# Targets: SdcNetwork.cc (findPin, findNet, findInstance, busName,
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# escapeDividers, escapeBrackets, portDirection, findPortsMatching,
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# portBitCount, fromIndex, toIndex, hasMember, memberIterator,
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# findBusBit, isBus, isBundle, name, groupBusPorts)
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# ParseBus.cc (parseBusName with range [0:7], subscript [*],
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# simple [0], isBusName, escapeChars)
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# ConcreteNetwork.cc (findPort, findBusBit, makeBusPort, groupBusPorts,
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# busName, isBus, isBundle, fromIndex, toIndex, portBitCount,
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# hasMember, findMember, memberIterator, size)
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# Network.cc (findPortsMatching with bus ranges, busIndexInRange,
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# hasMembers, setPathDivider, setPathEscape)
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../verilog/test/verilog_complex_bus_test.v
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link_design verilog_complex_bus_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_a[*]}]
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set_input_delay -clock clk 0 [get_ports {data_b[*]}]
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set_output_delay -clock clk 0 [get_ports {result[*]}]
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set_output_delay -clock clk 0 [get_ports carry]
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set_output_delay -clock clk 0 [get_ports overflow]
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set_input_transition 0.1 [get_ports {data_a[*] data_b[*] clk}]
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#---------------------------------------------------------------
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# Test bus range queries [from:to]
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# Exercises: parseBusName is_range path, findPortsMatching range path
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#---------------------------------------------------------------
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puts "--- bus range queries ---"
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# Query using range notation
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set range_ports [get_ports {data_a[0:3]}]
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puts "data_a\[0:3\] ports: [llength $range_ports]"
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set range_ports2 [get_ports {data_a[4:7]}]
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puts "data_a\[4:7\] ports: [llength $range_ports2]"
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set range_ports3 [get_ports {result[0:3]}]
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puts "result\[0:3\] ports: [llength $range_ports3]"
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# Reverse range (exercises from > to swap in findPortsMatching)
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set rev_range [get_ports {data_b[7:0]}]
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puts "data_b\[7:0\] ports: [llength $rev_range]"
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#---------------------------------------------------------------
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# Test wildcard subscript queries
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# Exercises: parseBusName subscript_wild path
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#---------------------------------------------------------------
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puts "--- wildcard subscript queries ---"
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set wild_a [get_ports {data_a[*]}]
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puts "data_a\[*\] ports: [llength $wild_a]"
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set wild_b [get_ports {data_b[*]}]
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puts "data_b\[*\] ports: [llength $wild_b]"
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set wild_r [get_ports {result[*]}]
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puts "result\[*\] ports: [llength $wild_r]"
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#---------------------------------------------------------------
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# Test individual bit queries
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# Exercises: parseBusName simple subscript path
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#---------------------------------------------------------------
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puts "--- individual bit queries ---"
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foreach bus {data_a data_b result} {
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foreach i {0 1 3 5 7} {
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set p [get_ports "${bus}\[$i\]"]
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set dir [get_property $p direction]
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set fn [get_full_name $p]
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puts "${bus}\[$i\]: dir=$dir name=$fn"
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}
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}
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#---------------------------------------------------------------
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# Test non-bus scalar port queries
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# Exercises: parseBusName returns is_bus=false
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#---------------------------------------------------------------
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puts "--- scalar port queries ---"
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set clk_p [get_ports clk]
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puts "clk: [get_full_name $clk_p] dir=[get_property $clk_p direction]"
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set carry_p [get_ports carry]
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puts "carry: [get_full_name $carry_p] dir=[get_property $carry_p direction]"
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set ovfl_p [get_ports overflow]
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puts "overflow: [get_full_name $ovfl_p] dir=[get_property $ovfl_p direction]"
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#---------------------------------------------------------------
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# Test get_ports with glob patterns on bus ports
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# Exercises: findPortsMatching with non-bus patterns
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#---------------------------------------------------------------
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puts "--- glob patterns on bus ports ---"
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set data_ports [get_ports data*]
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puts "data* ports: [llength $data_ports]"
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set all_ports [get_ports *]
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puts "all ports: [llength $all_ports]"
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set star_result [get_ports result*]
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puts "result* ports: [llength $star_result]"
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set question_ports [get_ports {?arry}]
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puts "?arry ports: [llength $question_ports]"
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#---------------------------------------------------------------
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# Test get_pins with bus-style patterns across hierarchy
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# Exercises: findPinsMatching, findInstPinsMatching
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#---------------------------------------------------------------
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puts "--- pin queries on bus design ---"
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set all_pins [get_pins */*]
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puts "all flat pins: [llength $all_pins]"
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set hier_pins [get_pins -hierarchical *]
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puts "hierarchical pins: [llength $hier_pins]"
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# Pin patterns matching specific ports
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set a_pins [get_pins */A]
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puts "*/A pins: [llength $a_pins]"
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set z_pins [get_pins */Z]
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puts "*/Z pins: [llength $z_pins]"
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set zn_pins [get_pins */ZN]
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puts "*/ZN pins: [llength $zn_pins]"
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set ck_pins [get_pins */CK]
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puts "*/CK pins: [llength $ck_pins]"
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set d_pins [get_pins */D]
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puts "*/D pins: [llength $d_pins]"
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set q_pins [get_pins */Q]
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puts "*/Q pins: [llength $q_pins]"
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# Pins on specific instances by pattern
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set buf_a_pins [get_pins buf_a*/*]
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puts "buf_a* pins: [llength $buf_a_pins]"
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set and_pins [get_pins and*/*]
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puts "and* pins: [llength $and_pins]"
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set reg_pins [get_pins reg*/*]
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puts "reg* pins: [llength $reg_pins]"
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#---------------------------------------------------------------
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# Test get_nets with bus patterns
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# Exercises: findNetsMatching with bus names
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#---------------------------------------------------------------
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puts "--- net queries on bus design ---"
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set all_nets [get_nets *]
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puts "all nets: [llength $all_nets]"
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set stage1_nets [get_nets stage1*]
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puts "stage1* nets: [llength $stage1_nets]"
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set stage2_nets [get_nets stage2*]
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puts "stage2* nets: [llength $stage2_nets]"
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set hier_nets [get_nets -hierarchical *]
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puts "hierarchical nets: [llength $hier_nets]"
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#---------------------------------------------------------------
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# Test get_cells with patterns in bus design
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# Exercises: findInstancesMatching patterns
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#---------------------------------------------------------------
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puts "--- cell queries on bus design ---"
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set all_cells [get_cells *]
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puts "total cells: [llength $all_cells]"
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set buf_cells [get_cells buf*]
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puts "buf* cells: [llength $buf_cells]"
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set and_cells [get_cells and*]
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puts "and* cells: [llength $and_cells]"
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set reg_cells [get_cells reg*]
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puts "reg* cells: [llength $reg_cells]"
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set or_cells [get_cells or*]
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puts "or* cells: [llength $or_cells]"
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# Filter on ref_name
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set buf_x1_cells [get_cells -filter "ref_name == BUF_X1" *]
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puts "BUF_X1 cells: [llength $buf_x1_cells]"
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set and2_cells [get_cells -filter "ref_name == AND2_X1" *]
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puts "AND2_X1 cells: [llength $and2_cells]"
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set dff_cells [get_cells -filter "ref_name == DFF_X1" *]
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puts "DFF_X1 cells: [llength $dff_cells]"
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#---------------------------------------------------------------
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# Test report_net on bus element nets
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# Exercises: net pin iteration on bus-connected nets
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#---------------------------------------------------------------
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puts "--- report_net on bus nets ---"
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foreach idx {0 3 7} {
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report_net "stage1\[$idx\]"
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puts "report_net stage1\[$idx\]: done"
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report_net "stage2\[$idx\]"
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puts "report_net stage2\[$idx\]: done"
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}
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# Non-bus internal nets
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report_net internal_carry
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puts "report_net internal_carry: done"
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report_net internal_overflow
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puts "report_net internal_overflow: done"
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#---------------------------------------------------------------
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# Test report_instance on various cells
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# Exercises: instancePinIterator, cell property queries
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#---------------------------------------------------------------
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puts "--- report_instance on bus cells ---"
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foreach inst {buf_a0 buf_a7 and0 and7 reg0 reg7 or_carry and_ovfl buf_carry buf_ovfl} {
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report_instance $inst
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puts "report_instance $inst: done"
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}
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#---------------------------------------------------------------
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# Test liberty library queries with patterns
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# Exercises: findCellsMatching on liberty libraries
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#---------------------------------------------------------------
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puts "--- liberty library queries ---"
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set libs [get_libs *]
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puts "libraries: [llength $libs]"
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set all_lib_cells [get_lib_cells */*]
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puts "all lib cells: [llength $all_lib_cells]"
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set nand_lib [get_lib_cells */NAND*]
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puts "NAND* lib cells: [llength $nand_lib]"
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set nor_lib [get_lib_cells */NOR*]
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puts "NOR* lib cells: [llength $nor_lib]"
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set mux_lib [get_lib_cells */MUX*]
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puts "MUX* lib cells: [llength $mux_lib]"
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set dff_lib [get_lib_cells */DFF*]
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puts "DFF* lib cells: [llength $dff_lib]"
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set aoi_lib [get_lib_cells */AOI*]
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puts "AOI* lib cells: [llength $aoi_lib]"
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set oai_lib [get_lib_cells */OAI*]
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puts "OAI* lib cells: [llength $oai_lib]"
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#---------------------------------------------------------------
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# Test all_registers with bus design
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#---------------------------------------------------------------
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puts "--- registers in bus design ---"
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set regs [all_registers]
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puts "all_registers: [llength $regs]"
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set reg_data [all_registers -data_pins]
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puts "register data_pins: [llength $reg_data]"
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set reg_clk [all_registers -clock_pins]
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puts "register clock_pins: [llength $reg_clk]"
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set reg_out [all_registers -output_pins]
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puts "register output_pins: [llength $reg_out]"
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#---------------------------------------------------------------
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# Test timing with bus paths
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# Exercises: full timing traversal through bus nets
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#---------------------------------------------------------------
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puts "--- timing analysis ---"
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report_checks
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report_checks -path_delay min
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report_checks -from [get_ports {data_a[0]}] -to [get_ports {result[0]}]
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report_checks -from [get_ports {data_a[7]}] -to [get_ports {result[7]}]
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report_checks -from [get_ports {data_a[7]}] -to [get_ports carry]
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report_checks -from [get_ports {data_b[6]}] -to [get_ports overflow]
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -endpoint_count 5
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report_checks -group_count 3
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