191 lines
6.1 KiB
Plaintext
191 lines
6.1 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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--- Test 1: SDC namespace hierarchical queries ---
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sdc ports: 6
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sdc port clk dir=input
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sdc port in1 dir=input
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sdc port in2 dir=input
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sdc port in3 dir=input
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sdc port out1 dir=output
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sdc port out2 dir=output
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sdc cells: 7
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sdc sub* cells: 2
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sdc buf* cells: 3
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sdc hier cells: 11
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sdc hier *buf*: 5
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sdc hier *and*: 2
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sdc flat pins: 20
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sdc hier pins: 30
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sdc sub1/* pins: 3
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sdc sub2/* pins: 3
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sdc nets: 11
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sdc w* nets: 5
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sdc hier nets: 19
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Warning 361: network_sdc_adapt_deep.tcl line 1, net 'sub*/*' not found.
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sdc hier sub*/* nets: 0
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No paths found.
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Startpoint: in2 (input port clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.06 0.06 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.09 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.11 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.14 v sub2/buf_gate/Z (BUF_X1)
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0.02 0.16 v buf_out2/Z (BUF_X1)
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0.00 0.16 v out2 (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in3 (in)
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0.04 0.04 ^ sub2/and_gate/ZN (AND2_X1)
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0.02 0.07 ^ sub2/buf_gate/Z (BUF_X1)
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0.01 0.07 v inv1/ZN (INV_X1)
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0.00 0.07 v reg1/D (DFF_X1)
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0.07 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.07 data arrival time
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---------------------------------------------------------
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0.07 slack (MET)
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--- Test 2: register queries ---
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all_registers: 1
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register data_pins: 1
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register clock_pins: 1
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register output_pins: 2
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register async_pins: 0
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--- Test 3: SDC namespace fanin/fanout ---
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sdc fanin to out1: 5
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sdc fanin to out2: 18
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sdc fanout from in1: 17
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sdc fanout from in2: 15
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sdc fanout from in3: 11
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sdc fanin cells to out1: 3
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sdc fanin cells to out2: 2
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sdc fanout endpoints from in1: 0
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sdc fanout endpoints from in3: 0
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--- Test 4: namespace switching ---
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iteration 0: sdc_cells=7 sta_cells=11
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iteration 1: sdc_cells=7 sta_cells=11
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iteration 2: sdc_cells=7 sta_cells=11
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--- Test 5: specific pin queries in SDC ---
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sdc pin buf_in/A: dir=input full_name=buf_in/A
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sdc pin buf_in/Z: dir=output full_name=buf_in/Z
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sdc pin inv1/A: dir=input full_name=inv1/A
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sdc pin inv1/ZN: dir=output full_name=inv1/ZN
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sdc pin reg1/D: dir=input full_name=reg1/D
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sdc pin reg1/CK: dir=input full_name=reg1/CK
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sdc pin reg1/Q: dir=output full_name=reg1/Q
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sdc deep pin sub1/and_gate/A1: dir=input
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sdc deep pin sub1/and_gate/ZN: dir=output
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sdc deep pin sub1/buf_gate/Z: dir=output
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sdc deep pin sub2/and_gate/A1: dir=input
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sdc deep pin sub2/buf_gate/Z: dir=output
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--- Test 6: SDC with bus design ---
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sdc bus design ports: 11
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sdc data_in[*]: 4
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sdc data_out[*]: 4
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sdc data_in[0]: dir=input
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sdc data_in[1]: dir=input
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sdc data_in[2]: dir=input
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sdc data_in[3]: dir=input
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sdc bus design cells: 12
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sdc bus design nets: 19
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.03 0.08 v and0/ZN (AND2_X1)
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0.00 0.08 v reg0/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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